BTC FPGA Miner Challenge  Best Hashrate, Lowest power per hash
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For 10 years, poor FPGA BTC mining implementations, with excessively slow, power hungry designs. Researchers presented dozens of papers on how to make this better. This is your chance to get it right. Read this paper https://ieeexplore.ieee.org/document/9691379, then https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9151160 and look at their Verilog here github.com/archlabnaist/DoubleCMESHA256 to get a good understanding about state of the art FPGA BTC mining with verilog. Then apply that to YOUR FORK of the old standard in https://github.com/fpgaminer/OpenSourceFPGABitcoinMiner with an updated proxy for getwork.
Clues follow to make FPGA BTC mining faster, smaller, and lower power, so that you will have REAL bragging rights for the fastest, smallest, lowest power FGPA miners.
1) The SHA256 compression is seeded with 256 bits of very random constants and forms a large shift register as the seed text and W[n] expansion pass results are mixed in during the next 64+64 rounds of the 2nd and 3rd SHA256 passes. The DoubleCMESHA256 paper shows you how to factor unnecessary work away for a leaner pipelined design. But it misses removing a completely wasteful group of registers doing a simple shift operation. As such the minimum fully unrolled digest requires about 256*(64+64)=32,768 registers of which 25% capture the rounds compression results, 75% are simply copying data in the shift operation. See Github nalex87/VerilogSHA2561
2) Heavy pipelining register setup and hold times become a significant part of each clock cycle and dominate as the designer tries to reach excessively high clock rates. This fails when high bandwidth, low resource use, and low power are three critical optimization metrics necessary for successful reconfigurable computing projects. EVERY CLOCK on pipeline registers burns power, so a power optimal design should have combinatorial logic with the least routing losses and fewest clock cycles per hash. There is a sweet spot in this combinatorial length, with additional wasted power when it becomes too long and cascaded gates oscillate with multiple uncertain inputs.
3) Cascaded expressions create unnecessary time delays that may not be recognized and optimized out by the tools. Expressions like A + B + C + D + E + F + G + H (7 serial adder delays) should be written as (((A + B) + (C + D)) + ((E + F) + (G + H))) (3 serial adder delays) with each matched addition pairs in parallel. Most synthesized arithmetic expressions are done with 32 or 42 full adder compressors (A+B+Carry) which even in tree form can still generate some uncertainty oscillations. A lower power FPGA design with 6input LUT's and a hardware carry circuit is to implement 63 or 73 full adder compressors when there are three or more sequential operators to combine in parallel ... plus carry lookahead. Carefully map out and optimize latency paths caused by cascaded operations, and carry propagation paths. Use floor planning to minimize routing latencies.
4) Optimizations to extract the last few percent of bandwidth, resource, power optimization is to take word wide synthesis of expressions completely out of the verilog, and reduce each bit lane down to ANF with shared ANF product terms across all expressions. Specialized synthesis and floor planning.
5) Gray code nonce and other counters, stable lower peak currents at edges.
Best winner with averages from Xilinx XC7Z010, Altera 10M08 Dev Kit, GOWIN GW1NRUV9 (Tang Nano 9K) with RPI Pico controller. Weighted 10% speed, 10% power, each FPGA vendor, real mining with all three boards concurrently served by the RPI controller  20% solo mining, 20% pool mining for 12 hours each (report mining average and total hashes). Show your wiring diagram for concurrent mining in your github ReadMe page report.
Claim YOUR best engineer bragging rights?
Post your github link as your contest entry graphic. Only ONE entry per team. Nonconforming entries will be rejected
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