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    5,670 FPGA Verilog VHDL работ(-а,-ы) найдено, цены указаны в USD
    Project for Pavlo H. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)
    Project for Mykyta M. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)

    Имеется проект VHDL, необходимо процессы вынести в отдельные компоненты без потери функциональности и работоспособности тестбенча.

    $35 (Avg Bid)
    $35 Ср. заявка
    1 заявок(-ки)
    $111 Ср. заявка
    1 заявок(-ки)

    Разработка системы Формирования звуковых оповещений на основе FPGA,(Development of a system for generating sound notifications based on FPGA.)

    $38 (Avg Bid)
    $38 Ср. заявка
    3 заявок(-ки)
    Project for Sergey G. Завершено left

    Здравствуйте, Sergey G.! Я обратил внимание на ваш профиль и хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $35 (Avg Bid)
    $35 Ср. заявка
    1 заявок(-ки)
    Project for Oleksandr S. Завершено left

    Здравствуйте, Clevermindolex! Хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $30 (Avg Bid)
    $30 Ср. заявка
    1 заявок(-ки)

    Цветомузыка. Адресная светодиодная лента, фильтр по частотам (высокие, средние, низкие), в зависимости от громкости и частоты мигает лента разными цветами

    $17 (Avg Bid)
    $17 Ср. заявка
    1 заявок(-ки)

    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

    $23 (Avg Bid)
    $23 Ср. заявка
    4 заявок(-ки)
    vivado xilinx expert needed -- 3 6 дней(-я) left
    ПОДТВЕРЖДЕН

    i want long term employee. need to prepare report also. if you are expert in verilog, vhdl. please bid here

    $34 (Avg Bid)
    $34 Ср. заявка
    4 заявок(-ки)
    vivado xilinx expert needed -- 2 6 дней(-я) left
    ПОДТВЕРЖДЕН

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $5 / hr (Avg Bid)
    $5 / hr Ср. заявка
    1 заявок(-ки)
    NANDFLASH CONTROLLER FOR FPGA 6 дней(-я) left

    I want a Nand flash controller for FPGA, details in chat.

    $44 (Avg Bid)
    $44 Ср. заявка
    1 заявок(-ки)
    verilog project 6 дней(-я) left

    build calculator will be tested with 1 short question before hiring. It should take less than 15 minutes. Then I will mail you the PDF project files and we can get started. bid if you are ready.

    $971 (Avg Bid)
    $971 Ср. заявка
    17 заявок(-ки)
    FPGA project 9 дней(-я) left

    Hi Abdelhak T., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $2 / hr (Avg Bid)
    $2 / hr Ср. заявка
    1 заявок(-ки)
    Need someone very good in Verilog 5 дней(-я) left
    ПОДТВЕРЖДЕН

    I need someone very good in verilog. I will share more details on chat.

    $31 / hr (Avg Bid)
    $31 / hr Ср. заявка
    6 заявок(-ки)
    VHDL Program 5 дней(-я) left

    I have a source code and I need testbench for the code

    $61 (Avg Bid)
    $61 Ср. заявка
    2 заявок(-ки)
    FFT using verilog in VIVADO 5 дней(-я) left

    [войдите, чтобы посмотреть URL] using verilog in vivado 2. 8 Input 3. Real time input 4. Should reduce power and area consumption

    $93 (Avg Bid)
    $93 Ср. заявка
    1 заявок(-ки)
    Ultrasoinc rader in Verilog 8 дней(-я) left

    Hi Mohamed Sheriff M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $65 (Avg Bid)
    $65 Ср. заявка
    1 заявок(-ки)
    digital design 5 дней(-я) left

    Design an FSM that has an input X and an output Y . Whenever X changes from 0 to 1, Y should become 1 for two clock cycles and then return to 0 – even if X is still 1. 2. Design an FSM with no inputs and three outputs x, y, and z. The bit sequence x yz should always cycle through the following value: 000, 001, 010, 100, (repeat) I only need to write one Verilog file containing both the modu...

    $30 (Avg Bid)
    $30 Ср. заявка
    2 заявок(-ки)
    $120 Ср. заявка
    8 заявок(-ки)
    Digital electronics 4 дней(-я) left

    These are the topics of the course::: define the three levels of abstraction used in digital design design digital gates using NMOS, PMOS and CMOS logic families that implement boolean functions define the voltage transfer characteristics of a digital inverter desgin MUXes, latches and flip-flops using CMOS logic design linear feedback shift registers (LFSRs) that produce pseudo-random bit patter...

    $16 / hr (Avg Bid)
    $16 / hr Ср. заявка
    9 заявок(-ки)
    Verilog Design 4 дней(-я) left

    I need help with my Verilog project. Its a bit hard time for me, please bid if you can assist me with short time

    $20 - $40
    Скрытый
    $20 - $40
    4 заявок(-ки)
    verilog coding and simulation 4 дней(-я) left

    emulate my current verilog code.

    $154 (Avg Bid)
    $154 Ср. заявка
    14 заявок(-ки)
    Embedded Systems FPGA Project Assistance 3 дней(-я) left
    ПОДТВЕРЖДЕН

    We are from an IT consulting firm and an online tutoring company One of our client is in need of assistance in Embedded Systems FPGA

    $8 / hr (Avg Bid)
    $8 / hr Ср. заявка
    2 заявок(-ки)
    Electrical Engineers Required -- 2 3 дней(-я) left
    ПОДТВЕРЖДЕН

    I am running a company, i have team of electrical engineers in different domains. Due to heavy work flow i need to extend my team so i need electrical engineers in different domains (, Electrical power Engineering, Verilog and VDHL expert).

    $512 (Avg Bid)
    $512 Ср. заявка
    11 заявок(-ки)
    Ethereum bitstream for VCU1525 FPGA 2 дней(-я) left
    ПОДТВЕРЖДЕН

    I need bitstream for my card VCU1525 it has 64 GB of ram,need good hash rate. freelancer will deploy bitstream using vivado to my card and i will test its hashing rate and [войдите, чтобы посмотреть URL] i need the miner application to. also i need long term support,also write the word VCU in end of bid.

    $750 (Avg Bid)
    $750 Ср. заявка
    1 заявок(-ки)
    Verilog Coding Task. 2 дней(-я) left
    ПОДТВЕРЖДЕН

    Hi I am looking for Verilog Coding expert for a task. I will share more details through chat.

    $23 (Avg Bid)
    $23 Ср. заявка
    5 заявок(-ки)

    I am interested to work on a long term research project where I need to find a new robust method (Approach) in the area of Resource Constrained Devices with Machine/Deep Learning for memory optimization, algorithm optimization, deep compression using pruning and quantization. I am open to use Arm Cortex, ESP32, or an FPGA for hardware acceleration. These embedded system have limited power, memory...

    $35 / hr (Avg Bid)
    $35 / hr Ср. заявка
    14 заявок(-ки)
    verilog sram bist 2 дней(-я) left

    I need an expert to emulate my current Verilog code.

    $161 (Avg Bid)
    $161 Ср. заявка
    6 заявок(-ки)
    Verilog Coding Task 2 дней(-я) left

    Hi I am looking for Verilog Coding expert for a task. I will share more details through chat.

    $27 (Avg Bid)
    $27 Ср. заявка
    6 заявок(-ки)
    Verilog Coding 2 дней(-я) left
    ПОДТВЕРЖДЕН

    Hi I am looking for Verilog Coding expert for a task. I will share more details through chat.

    $31 (Avg Bid)
    $31 Ср. заявка
    4 заявок(-ки)
    vivado xilinx expert needed 1 день left
    ПОДТВЕРЖДЕН

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $146 (Avg Bid)
    $146 Ср. заявка
    9 заявок(-ки)
    Testbench in VHDL 1 день left

    I have a source code and I want the testbench code for it

    $47 (Avg Bid)
    $47 Ср. заявка
    2 заявок(-ки)

    i need some help which is related to verilog structure coding

    $16 (Avg Bid)
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    3 заявок(-ки)
    Verilog Alarm Clock 22 часов(-а) left
    ПОДТВЕРЖДЕН

    Design the control logic for an alarm clock (for simulation purposes 20ns simulation = 1 minute real time –this can be adjusted somewhat for simulation purposes). a) Use multiple input signals (alarm set input, the snooze, and the alarm time). b) The design will contain one output (Alarm_On). A logic high at the output represents the alarm being “on”. c) An input will be used ...

    $71 (Avg Bid)
    $71 Ср. заявка
    8 заявок(-ки)
    vivado expert needed -- 2 21 часов(-а) left
    ПОДТВЕРЖДЕН

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $104 (Avg Bid)
    $104 Ср. заявка
    2 заявок(-ки)
    vivado expert needed 19 часов(-а) left
    ПОДТВЕРЖДЕН

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $4 / hr (Avg Bid)
    $4 / hr Ср. заявка
    2 заявок(-ки)
    Vhdl project -- 4 19 часов(-а) left
    ПОДТВЕРЖДЕН

    I need some clarification on vhdl

    $125 (Avg Bid)
    $125 Ср. заявка
    13 заявок(-ки)
    need help with vhdl 9 часов(-а) left

    Vending Machine Purpose: To use different acquired logic designs To gain experience of team work To design a VHDL based soda machine To test the design on the [войдите, чтобы посмотреть URL] site Tools: Compiler and testbench tools on [войдите, чтобы посмотреть URL]

    $21 (Avg Bid)
    $21 Ср. заявка
    3 заявок(-ки)
    Need an expert in Verilog 8 часов(-а) left

    Need an expert in Verilog . Need to familiar designing lowest possible latency systems

    $19 (Avg Bid)
    $19 Ср. заявка
    1 заявок(-ки)
    Verilog work 6 часов(-а) left

    Need someone who is fluent with Verilog code. A simple hexadecimal calculator will have to be coded. Need it done quick.

    $22 (Avg Bid)
    $22 Ср. заявка
    3 заявок(-ки)
    Digital Electronics 3 часов(-а) left
    ПОДТВЕРЖДЕН

    CMOS logic gates, digital circuit design using Verilog HDL and logic synthesis, clock distribution, digital circuit implementations and verification, digital memory and signalling technologies.

    $92 (Avg Bid)
    $92 Ср. заявка
    14 заявок(-ки)
    FPGA Design Project Завершено left

    Please see attached pdf file to get complete details related to this task. This required template has been added in zip file.....

    $87 (Avg Bid)
    $87 Ср. заявка
    7 заявок(-ки)

    Looking for Linux Kernel developers And FPGA developers to port the Mister Project Linux Kernel and U-Boot of DE10 Nano to the Xilinix Ultra96-V2 Zynq UltraScale+ ZU3EG. Once completed we need assistance porting of the existing FPGA cores of Mister Project to the zu3. Mister Project Linux Kernel: [войдите, чтобы посмотреть URL] Mister Project U-Boot: [войдите, чтобы посмотреть URL] [войдите, ...

    $548 (Avg Bid)
    $548 Ср. заявка
    5 заявок(-ки)

    You have a VHDL code and you need to describe it. I would provide example

    $19 (Avg Bid)
    $19 Ср. заявка
    8 заявок(-ки)

    Looking for Linux developers And FPGA developers to port the Mister Project Linux Kernel of DE10 Nano to the Xilinix Ultra96-V2 Zynq UltraScale+ ZU3EG. Once completed we need porting of Current developed D10 Nano cores to the zu3.

    $583 (Avg Bid)
    $583 Ср. заявка
    3 заявок(-ки)

    I need the help of someone who could help me propose and implement an algorithm using constraints programming methods that supports formal verification of digital models that can be used on hardware models in VHDL , verilog, e.t.c, its quite urgent please, your help would be highly appreciated

    $132 (Avg Bid)
    $132 Ср. заявка
    8 заявок(-ки)

    Hi, this project will require you to use verilog and basys3 board and logic analyzer to do the work. Contact me if you are an expert in this.

    $50 (Avg Bid)
    $50 Ср. заявка
    5 заявок(-ки)
    Project for Muhammad B. 15 часов(-а) left

    Hi binyameen i have lab report in vhdl can you work in it

    $10 (Avg Bid)
    $10 Ср. заявка
    1 заявок(-ки)