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    4,058 assemblyx86 verilog vhdl работ(-а,-ы) найдено, цены указаны в USD
    Project for Pavlo H. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)
    Project for Mykyta M. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)

    Имеется проект VHDL, необходимо процессы вынести в отдельные компоненты без потери функциональности и работоспособности тестбенча.

    $35 (Avg Bid)
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    Разработка системы Формирования звуковых оповещений на основе FPGA,(Development of a system for generating sound notifications based on FPGA.)

    $38 (Avg Bid)
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    3 заявок(-ки)
    Project for Sergey G. Завершено left

    Здравствуйте, Sergey G.! Я обратил внимание на ваш профиль и хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $35 (Avg Bid)
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    1 заявок(-ки)
    Project for Oleksandr S. Завершено left

    Здравствуйте, Clevermindolex! Хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $30 (Avg Bid)
    $30 Ср. заявка
    1 заявок(-ки)

    Цветомузыка. Адресная светодиодная лента, фильтр по частотам (высокие, средние, низкие), в зависимости от громкости и частоты мигает лента разными цветами

    $17 (Avg Bid)
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    1 заявок(-ки)

    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

    $23 (Avg Bid)
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    4 заявок(-ки)
    VHDL project 6 дней(-я) left

    Design a 4-bit sequential multiplier using VHDL based on the system controller approach. The circuit takes 2 4-bit numbers (M4M3M2M1) (the multiplicand) and (N4N3N2N1)(the multiplier), and a START signal; and produces their product (R8R7R6R5R4R3R2R1) and a DONE signal. The operation starts when START signal is asserted. The START signal must below for at least one clock cycle after DONE is asserte...

    $153 (Avg Bid)
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    6 заявок(-ки)

    have been struggling with this lab for a long time, very hard for me, need assistance, related file is provided

    $136 (Avg Bid)
    Срочный
    $136 Ср. заявка
    2 заявок(-ки)
    verilog code in vivado 5 дней(-я) left

    1. Need a verilog code for a project 2. Need a brief explanation of the code and demonstration

    $13 (Avg Bid)
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    1 заявок(-ки)
    vivado xilinx expert needed -- 3 5 дней(-я) left
    ПОДТВЕРЖДЕН

    i want long term employee. need to prepare report also. if you are expert in verilog, vhdl. please bid here

    $37 (Avg Bid)
    $37 Ср. заявка
    5 заявок(-ки)
    vivado xilinx expert needed -- 2 5 дней(-я) left
    ПОДТВЕРЖДЕН

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $5 / hr (Avg Bid)
    $5 / hr Ср. заявка
    1 заявок(-ки)
    verilog project 4 дней(-я) left

    build calculator will be tested with 1 short question before hiring. It should take less than 15 minutes. Then I will mail you the PDF project files and we can get started. bid if you are ready.

    $999 (Avg Bid)
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    Need someone very good in Verilog 4 дней(-я) left
    ПОДТВЕРЖДЕН

    I need someone very good in verilog. I will share more details on chat.

    $31 / hr (Avg Bid)
    $31 / hr Ср. заявка
    6 заявок(-ки)
    VHDL Program 4 дней(-я) left

    I have a source code and I need testbench for the code

    $61 (Avg Bid)
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    2 заявок(-ки)
    FFT using verilog in VIVADO 4 дней(-я) left

    [войдите, чтобы посмотреть URL] using verilog in vivado 2. 8 Input 3. Real time input 4. Should reduce power and area consumption

    $93 (Avg Bid)
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    Ultrasoinc rader in Verilog 7 дней(-я) left

    Hi Mohamed Sheriff M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $65 (Avg Bid)
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    1 заявок(-ки)
    digital design 4 дней(-я) left

    Design an FSM that has an input X and an output Y . Whenever X changes from 0 to 1, Y should become 1 for two clock cycles and then return to 0 – even if X is still 1. 2. Design an FSM with no inputs and three outputs x, y, and z. The bit sequence x yz should always cycle through the following value: 000, 001, 010, 100, (repeat) I only need to write one Verilog file containing both the modu...

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    2 заявок(-ки)
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    Digital electronics 3 дней(-я) left

    These are the topics of the course::: define the three levels of abstraction used in digital design design digital gates using NMOS, PMOS and CMOS logic families that implement boolean functions define the voltage transfer characteristics of a digital inverter desgin MUXes, latches and flip-flops using CMOS logic design linear feedback shift registers (LFSRs) that produce pseudo-random bit patter...

    $16 / hr (Avg Bid)
    $16 / hr Ср. заявка
    9 заявок(-ки)
    Verilog Design 3 дней(-я) left

    I need help with my Verilog project. Its a bit hard time for me, please bid if you can assist me with short time

    $20 - $40
    Скрытый
    $20 - $40
    4 заявок(-ки)
    verilog coding and simulation 2 дней(-я) left

    emulate my current verilog code.

    $154 (Avg Bid)
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    14 заявок(-ки)
    Electrical Engineers Required -- 2 2 дней(-я) left
    ПОДТВЕРЖДЕН

    I am running a company, i have team of electrical engineers in different domains. Due to heavy work flow i need to extend my team so i need electrical engineers in different domains (, Electrical power Engineering, Verilog and VDHL expert).

    $519 (Avg Bid)
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    12 заявок(-ки)
    Verilog Coding Task. 1 день left
    ПОДТВЕРЖДЕН

    Hi I am looking for Verilog Coding expert for a task. I will share more details through chat.

    $23 (Avg Bid)
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    5 заявок(-ки)
    verilog sram bist 22 часов(-а) left

    I need an expert to emulate my current Verilog code.

    $161 (Avg Bid)
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    6 заявок(-ки)
    Verilog Coding Task 17 часов(-а) left

    Hi I am looking for Verilog Coding expert for a task. I will share more details through chat.

    $27 (Avg Bid)
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    6 заявок(-ки)
    Verilog Coding 15 часов(-а) left
    ПОДТВЕРЖДЕН

    Hi I am looking for Verilog Coding expert for a task. I will share more details through chat.

    $31 (Avg Bid)
    $31 Ср. заявка
    4 заявок(-ки)
    vivado xilinx expert needed 4 часов(-а) left
    ПОДТВЕРЖДЕН

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $145 (Avg Bid)
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    10 заявок(-ки)
    Testbench in VHDL Заканчивающийся left

    I have a source code and I want the testbench code for it

    $47 (Avg Bid)
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    2 заявок(-ки)
    need help in verilog stuff Завершено left

    i need some help which is related to verilog structure coding

    $16 (Avg Bid)
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    3 заявок(-ки)
    Verilog Alarm Clock Завершено left

    Design the control logic for an alarm clock (for simulation purposes 20ns simulation = 1 minute real time –this can be adjusted somewhat for simulation purposes). a) Use multiple input signals (alarm set input, the snooze, and the alarm time). b) The design will contain one output (Alarm_On). A logic high at the output represents the alarm being “on”. c) An input will be used ...

    $71 (Avg Bid)
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    vivado expert needed -- 2 Завершено left

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $103 (Avg Bid)
    $103 Ср. заявка
    2 заявок(-ки)
    vivado expert needed Завершено left

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $4 / hr (Avg Bid)
    $4 / hr Ср. заявка
    2 заявок(-ки)
    Vhdl project -- 4 Завершено left

    I need some clarification on vhdl

    $125 (Avg Bid)
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    need help with vhdl Завершено left

    Vending Machine Purpose: To use different acquired logic designs To gain experience of team work To design a VHDL based soda machine To test the design on the [войдите, чтобы посмотреть URL] site Tools: Compiler and testbench tools on [войдите, чтобы посмотреть URL]

    $21 (Avg Bid)
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    Need an expert in Verilog Завершено left

    Need an expert in Verilog . Need to familiar designing lowest possible latency systems

    $19 (Avg Bid)
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    1 заявок(-ки)
    Verilog work Завершено left

    Need someone who is fluent with Verilog code. A simple hexadecimal calculator will have to be coded. Need it done quick.

    $22 (Avg Bid)
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    3 заявок(-ки)
    Digital Electronics Завершено left

    CMOS logic gates, digital circuit design using Verilog HDL and logic synthesis, clock distribution, digital circuit implementations and verification, digital memory and signalling technologies.

    $91 (Avg Bid)
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    14 заявок(-ки)

    You have a VHDL code and you need to describe it. I would provide example

    $19 (Avg Bid)
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    8 заявок(-ки)

    I need the help of someone who could help me propose and implement an algorithm using constraints programming methods that supports formal verification of digital models that can be used on hardware models in VHDL , verilog, e.t.c, its quite urgent please, your help would be highly appreciated

    $132 (Avg Bid)
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    Hi, this project will require you to use verilog and basys3 board and logic analyzer to do the work. Contact me if you are an expert in this.

    $50 (Avg Bid)
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    Project for Muhammad B. Завершено left

    Hi binyameen i have lab report in vhdl can you work in it

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    Project for Muhammad A. Завершено left

    Hi Muhammad A., i have lab report in quartus vhdl can you work in it.

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    The booth multiplier circuit is from a research paper. I will give you the research paper.

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    5 заявок(-ки)
    Verilog coding on FPGA's Завершено left

    I need an expert who can do implement modular multiplication algorithms in Verilog and simulate their results to make a comparison in their speed of implementation, hardware consumed etc.

    $359 (Avg Bid)
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    23 заявок(-ки)
    Design an FPGA mesh architecture Завершено left

    I'm required to design this architecture using VHDL. This architecture also consists of hops.

    $110 (Avg Bid)
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    Robotic Expert Завершено left

    Hello freelancers, I am looking for an expert in VHDL/FPGA for an interesting project. The project is very small and I encourage new freelancers to place the bid. My budget is 30-40 AUD

    $82 (Avg Bid)
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    4 заявок(-ки)
    VHDL Expertss Завершено left

    Hello freelancers, I am looking for an expert in VHDL for an interesting project. The project is very small and I encourage new freelancers to place the bid. My budget is 30-40 AUD

    $44 (Avg Bid)
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    6 заявок(-ки)
    verilog, vhdl expert needed -- 3 Завершено left

    i want long term employee. i need to draw internal block diagram. if you are expert, please bid here

    $3 / hr (Avg Bid)
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    7 заявок(-ки)