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    3,281 design framer vhdl verilog работ(-а,-ы) найдено, цены указаны в USD

    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

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    Digital Systems 6 дней(-я) left

    I need a help with VHDL Design. Please reply me if you can help me with this. afte that i will share more details

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    Simulating Multiple Gates - Third installment (Verilog + C) 6 дней(-я) left
    ПОДТВЕРЖДЕН

    The first installment of the project dealt with the capability to simulate the actions of four very simple gate types, an INV gate, an AND gate, an OR gate and an XOR (exclusive or) gate. The second installment extended that capability by describing the simple logic gates using Verilog, but the Verilog was restricted to descriptions of circuits which only contained a single gate. For the third ins...

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    Project in system verilog 5 дней(-я) left
    ПОДТВЕРЖДЕН

    Build a project using system verilog

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    Work on VHDL Laboratory like Latches, Flip-flops and registers 4 дней(-я) left
    ПОДТВЕРЖДЕН

    Need to investigate the latches, flip-flops and the registers in VHDL laboratory work

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    I want to hire a person who has an experience in solving problems related to verilog in VLSI design(small work though),has to be experienced in handy usage of software like xilinx/[войдите, чтобы посмотреть URL] for the problem and other info.

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    (2) Random Examples must be created using System Verilog. The Examplesmust be simulated (Model Sim) and synthesized (SynplifyPro). Example figures attached. Results should be attached as a jpg or pdf.

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    Project for Ankita L. -- 2 6 дней(-я) left

    it a vhdl coding project I want it in 3 days max.

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    digital Alarm clock. I need it for my final project. Please let me know if anyone can do it in 20$. Lowest bit will be rewarded.

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    This Project is to investigate latches, flip-flops and registers. VHDL -- Quartus Prime Lite 18.1 Quartus. design simple processor

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    This Project is to investigate latches, flip-flops and registers. VHDL -- Quartus Prime Lite 18.1 Quartus.

    $15 (Avg Bid)
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    2 ставки
    Simulating Multiple Gates third installment c + verilog 3 дней(-я) left
    ПОДТВЕРЖДЕН

    The first installment of the project dealt with the capability to simulate the actions of four very simple gate types, an INV gate, an AND gate, an OR gate and an XOR (exclusive or) gate. The second installment extended that capability by describing the simple logic gates using Verilog, but the Verilog was restricted to descriptions of circuits which only contained a single gate. For the third ins...

    $50 (Avg Bid)
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    16 ставки
    Design a clickable prototype (mobile + desktop) 2 дней(-я) left
    ПОДТВЕРЖДЕН

    Looking for an experienced designer (Sketch, Framer, Adobe) to create a clickable prototype for a responsive website (mobile + desktop) based on drawings. It's a regular e-commerce site but for digital products. We will send drawings during communication, but before we agree on the project. If you've read everything please start the proposal with your favourite movie name. You should ha...

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    Digital Logic Project 2 дней(-я) left

    hello, please if you can comment out the verilog code and the steps done, so we know how to explain it. also, i need this project to be done in exactly one week from today. thank you

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    Necesitamos Backend 1 день left

    Se requiere backend que tenga experiencia en: [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL] -Visual studio -Ionic -entyt framer -angular

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    electric engineering 8 часов(-а) left

    Need someone know well vhdl ............................. ............................. .............................

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    FPGA Implementation Завершено left

    FPGA Implementation of a 4-bit look-ahead carry adder - need to code in VHDL. BUDGET IS 20 CAD.

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    All code written in system verilog and the functions mod or divide not allowed Time should be displayed on the 6 digits of the seven segment displays (HHMMSS) -hours displayed in military time -when SW2=1, alarm is set and 6 digits display alarm time -when KEY0=0, the alarm is reset to 0, KEY0 takes priority over SW2 The alarm clock must be accurate, divide down the 50MHz clock at PIN_P11 as neces...

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    I will provide you with a list of 15 very basic questions about the VHDL language for FPGAs. I need you to answer them with a minimum of 100-200 words for each answer. Your answers will be put into a spreadsheet. Your answers need to have great spelling, grammar, and be 100% unique. I don't want any copy/paste answers, and I will be checking for duplicate content. This is an introductory j...

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    Neural network using Verilog -- 2 Завершено left

    I have a verilog project in which i have to implement neural network to recognize Amazon packages from the given binary matrix image. I already made most of the design code. I am new to verilog and need to finish the project till the final layout.

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    Neural network using Verilog Завершено left

    I have a verilog project in which i have to implement neural network to recognize Amazon packages from the given binary matrix image. I already made most of the design code. I am new to verilog and need to finish the project till the final layout.

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    Building a verilog game Завершено left

    Making a code for snake and ladder in verilog .

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    I need a professional engineer to help in writing a technical report with Verilog code

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    I need professional engineer to help in writing a technical report with Verilog code

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    VHDL HAMMING CODE Завершено left

    CREATE A HAMMING ENCODER, DECODER USING VHDL/VEROLOG

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    We are an IT consultant company and Online tutoring company One of our client needs assistance in Xilinx Vivado - Verilog Project Please bid if you have expertise in Verilog

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    Xilinx Vivado - Verilog Project Завершено left

    We are an IT consultant company and Online tutoring company One of our client needs assistance in Xilinx Vivado - Verilog Project Please bid if you have expertise in Verilog

    $3 / hr (Avg Bid)
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    VHDL project Завершено left

    Hi, I currently want to make a music visualizer to be displayed on a monitor using VHDL. The software is Xilinx Vivado. Please send me a message if you would like to further discuss this.

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    Verilog Netlist Enhancer Завершено left

    A utility that calculates the delay of a path taking into consideration the interconnect effects. The utility accepts a routed DEF file, the technology LEF and the library liberty file. The user has to specify the path cells in a file. A possible format for that file is: INPORT/x AND2_X1/a . . DFF_X2/D Instead of providing the path cells, provide the path starting and ending points. Some resourc...

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    Verilog experts needed Завершено left

    I need to create a snake game for my project using verilog on my basys 3 board. I have the codes for it but however the codes that I have is for a 12bits RGB VGA 640 x 480 display. I am using a 16bits RGB OLed 96 x 64 display. I'm having trouble to convert it over can you please help me with it? Or u can just write a completely new program for me too. Attached is the board and the Led is at t...

    $7 - $21
    $7 - $21
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    Verilog expert needed -- 2 Завершено left

    I need to create a snake game for my project using verilog on my basys 3 board. I have the codes for it but however the codes that I have is for a 12bits RGB VGA 640 x 480 display. I am using a 16bits RGB OLed 96 x 64 display. I'm having trouble to convert it over can you please help me with it? Or u can just write a completely new program for me too. Attached is the board and the Led is at t...

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    VGA CONTROLLER in VERILOG Завершено left

    I need a VGA Controller in verilog. Resolution 160 X 120. VGA controller needs to have its own memory. When the game is started the maze glyph will be loaded into the memory (will only have about 10 glyphs). The controller will need to loop through the shared memory with the 19,200 locations that will tell it the glyph locations and when the character sprite moves.

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    Verilog expert needed Завершено left

    I need to create a snake game for my project using verilog on my basys 3 board. I have the codes for it but however the codes that I have is for a 12bits RGB VGA 640 x 480 display. I am using a 16bits RGB OLed 96 x 64 display. I'm having trouble to convert it over can you please help me with it? Or u can just write a completely new program for me too. Attached is the board and the Led is at t...

    $44 (Avg Bid)
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    1 ставки
    Project for Aamir Sohail N. Завершено left

    Hi Aamir Sohail N., As we discussed, You may continue working on VHDL project I am offeriuing work at INR160/hr with 20 hours for working, so thta You get INR 3200/- as agreed.

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    Parking Meter Design in VHDL Завершено left

    1.A VHDL model for your Data Path consisting of the following sub-models as also presented and discussed in-class: [войдите, чтобы посмотреть URL] four digit BCD adder that adds to the count of seconds left in the accumulator the additional minutes(in seconds) being purchased by the 5/10/25 cents coins for 300/600/1500secs respectively This four digit adder should also be used to subtract 1 secon...

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    Basic VHDL coding needed for a project, described below

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    Create a project about a 128x3 (128 words, with 3 bits at each word) single-port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. •One side of the DIP switch clears the memory address (not the memory contents). •The depressing of the first push-button indicates a memory write...

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    In this lab assignment, you will design the top level, register file, control decoder, ALU (arithmetic logic unit), data memory, muxes (signal routing switches), lookup tables, and fetch unit (program counter plus instruction ROM) for your CPU. For this and future designs, we want the highest level of your design to be a schematic and [System]Verilog code... if you are intersted in let me know ....

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    Electronics design circuit Завершено left

    I have some design which are related to electronics. I want these digital design to be solved using vhdl. These task are pretty simple. i will provide you further details as you contact me

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    Job Description: We are looking for a UI/UX Designer who carries a passion for designing beautiful, intuitive experiences in complex, data-intensive web applications. Role & Responsibilities: • Solve complex interaction design problems and strive to create great customer experiences within our product offering. • Work across teams to create UI storyboards, wireframes, and concept d...

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    Build a project in system verilog to work as a convolution engine

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    Project for Majid A. -- 2 Завершено left

    (1) FSM WITH VHDL+ TESTBENCH ( TRUTH TABLE,KMAP AND CODE)

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    Design an FPGA ready CPU Tutorial Завершено left

    I need a small CPU project prepared, to teach and demonstrate CPU construction. It should be able to fit on an Intel Altera. It should use RISC. The key components are the ability to explain why cache's were chosen, why addressing was chosen, and what options existed. 8-bits. It should be built using blocks, such that I can remove a block, and code in my own block, and assuming all is good, w...

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    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory wr...

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    Build me an ALU using vhdl Завершено left

    Details will be provided upon in personal chat. Only experts apply, as I need product to be delivered asap.

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    SITUATION: I have a VHDL design for a custom processor + peripherals that needs to go into an FPGA. It passes functional simulation that uses VHDL testbenches. I am in the process of adding VHDL checkers. This design needs to pass timing simulation with a (soft) target frequency of 50 MHz, be programmed into an FPGA, and be verified using an off-the-shelf FPGA card. While I'm strong in digit...

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    Verilog content creation Завершено left

    Create Video tutorial of Verilog for students reference

    $8 / hr (Avg Bid)
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    Verilog Code for DE0-Nano board Завершено left

    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory wr...

    $50 (Avg Bid)
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    1 ставки