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    2,526 e1 framer verilog работ(-а,-ы) найдено, цены указаны в USD

    необходимо создать городской портал по примеру [войдите, чтобы посмотреть URL] еще пример [войдите, чтобы посмотреть URL] в нем должны присутствовать следующие разделы: Новости(автоматически копирующие новости с популярных новостных сайтов ) Работа вакансии/резюме Авто покупка/продажа/статьи яндекс карты пробки Недвижимость купля/продажа Баннерная система (реклама) Справка (погода, курсы ...

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    Создание веб-сайта Завершено left

    необходимо создать городской портал по примеру [войдите, чтобы посмотреть URL] в нем должны присутствовать следующие разделы: Новости(автоматически копирующие новости с популярных новостных сайтов ) Работа вакансии/резюме Авто покупка/продажа/статьи яндекс карты пробки Недвижимость купля/продажа Баннерная система (реклама) Справка (погода, курсы валют, справочник предприятий города с карт...

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    Переделка конвертера с С# на С/C++. Использование типовых пакетов linux. Работа с потоком E1/PRI, HDLC, LAPD, X25

    $777 (Avg Bid)
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    Выписать в отдельную таблицу по полям Город, название, телефон, e-mail, сайт информацию об оптовых клиентах по городам России со следующих 6 сайтов. Пример таблицы во вложении. [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL]

    $150 (Avg Bid)
    Гарантированный

    Looking for excel vba expert to help write a vba macro for following logic: Steps: Setting the period (first and last column where code should be executed) 1. First column = Today's date + E1 2. Last column = Today's date + F1 Push out logic 1. Match the AZs (E8:E24) to Gap/Excess (B63:B77) 2. For each matching AZs, if there is a excess (above 0, positive value) push the value in push/...

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    Crear VM con Issabel en VMware 6 дней(-я) left
    ПОДТВЕРЖДЕН

    Somos un call center argentino que trabaja con multicampaña. Necesitamos crear 3 VM (Maquinas virtuales) en un servidor Dell. En las 3 VM se deben instalar la versión mas reciente de Issabel (Central Telefónica). Debe esta bajo SO Linux. Parámetros: Configurar troncales y rutas salientes: Troncales: 1 Gateway synway GSM de 16 canales 1 Gateway Openvox GSM 12 canales...

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    Our company is seeking for a passionate UI/UX Freelancers who working directly with a multi-national team of accomplished software engineers in India, South Africa, Colombia, and the US. Our UI/UX Freelancers interact directly with other tech team members, as well as functional business managers and end users for the product around the globe. [Removed for encouraging offsite communication which is...

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    FIR filter Design using FPGA 5 дней(-я) left

    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

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    verilog design -- 2 4 дней(-я) left
    ПОДТВЕРЖДЕН

    I need to implement system verilog code design you will design a bit movement block. This block works with a 32 bit read and write interface, and can move data starting at any bit location. The block has two interfaces. One to read and write registers, another for the block to read and write memory, and a third interface for some status and completion information. The interface is defined with t...

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    verilog design 4 дней(-я) left
    ПОДТВЕРЖДЕН

    I need to implement system verilog code design you will design a bit movement block. This block works with a 32 bit read and write interface, and can move data starting at any bit location. The block has two interfaces. One to read and write registers, another for the block to read and write memory, and a third interface for some status and completion information. The interface is defined with t...

    $26 (Avg Bid)
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    Fix NEURAL NETWORK IN VERILOG 3 дней(-я) left

    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : fix neural network *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in training. *All of this should be printed in the ...

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    FPGA DESIGN ENGINEER 1 день left

    We are seeking 1 FPGA Design Engineer for our new product development. FPGA Design Engineer Responsibilities: • Completing implementation in RTL • Ensuring robust and complete timing constraints • Optimizing FPGA code to balance performance, area, power, complexity and timing • Determining and executing development, integration, bring-up and test plans. • Working closely ...

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    Create some wireframes 1 день left

    I have a web application which serves as an internal tool for my company. I want a UI/UX designer to take a look at it and revamp the design of it by creating some wireframes using a tool like Sketch or Framer X.

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    Eye pupil tracking Завершено left

    I would like to do project in human eye pupil tracking system for video sequence using Verilog in Xilinx spartan 6 FPGA. Here with attached my equirements Requirements: 1. Find the pupil center coordinates and radius for various eye's. 2. Coordinates should be constant intervals while tracking. 3. Only video sequence to be used.... Not for image. Kindly send me possibility of above …...

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    implementing 8-bit comparator Завершено left

    i need a 8-bit comparator characterizing overdrive, to be implemented on FPGA, using Verilog also I need the constrains file

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    FPGA/VHDL/Verilog Завершено left

    Looking for implementation of a Ethernet Tester, generating and analyzing Ethernet traffic at 1G and 10G. More details on PM. J

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    Camera development Завершено left

    Opal Kelly front panel, C++, Verilog, XEM6010. Must have experience with Opal Kelly front panel, since this project will be similar with the EVB100X-DEV. Same concept, but different sensor.

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    Building a simple (for now) banking app, a rough prototype already exists in Framer X, and we need a designer to make it actually look nice. The ideal candidate would be creating high fidelity, high quality designs of the described screens (or making the current ones look nice), with the necessary style guide, and component library. OSX user preferred for now (SF Pro font, SF Pro Text icons, iOS...

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    build opencl code Завершено left

    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : Build a deep neural network using some of approximate MAC UNIT, *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in traini...

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    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : Build a deep neural network using some of approximate MAC UNIT, *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in traini...

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    Clean, format and validate data Завершено left

    There are three data files 1. Organizers and Events Requirement Validate emails Remove records that do not have emails that validate Provide 2 files: a). File - with records that only contain validated emails b). File with old data - email not validated 2. Exporters Requirements a) Shorten Product Category Name - in all Product Category 1-7 columns Keep short name the same in all columns b) ...

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    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

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    Basement framer -- 2 Завершено left

    Need basement framed. Labor only — no materials needed. Should only take a day.

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    Basement framer Завершено left

    Need basement framed. Labor only — no materials needed.

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    3 ставки
    Need example code de-10 Завершено left

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    Project for Marina L. Завершено left

    I need an "and" keyword search program, that I will describe as if it is in Excel, but it doesn't need to be an Excel program. In Excel column A, and in each cell down to a maximum of about 850,000 rows, there will be a list of words 50 to 1000 characters long. For example: A2: cat dog rabbit mouse trap... A3: table chair stool lamp ... A4: car truck motorcycle parts ... A5: comp...

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    Your challenge: Deploy a working app to apple store in 10 days. By 8/17/19. If you do well, you will be given ALOT more opportunities and work. The app will have 6 pages and is very similar ot an e-commerce type of flow: 1. Email sign up 2. Ask a question 3. Show a special product (the most popular.. just 1 product) 4. Show product details. 5. Buy the product 6. Show a list of additional prod...

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    my project is about lipstick made from natural organic materials. High Quality My website in Vietnamese, you can make it with english than i give you the translation for vietnamese version I need the website easy to SEO with all tag / onpage SEO. + Chat and call button + Link to facebook pages, likes and share button + Faecbook pixels for facebook ads intergrated to action of users + Google ana...

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    Map page will be full map with 2 layer: Origin layer (from OSM) and KML layer KML layer will be provide as in attachment User interact with map will be similar to wikimapia in which user hover over a place it will light up (see attached image) when click to a place it will show custom content with link to forum custom content is similar like this http://wikimapia.org/#lang=vi&lat=20.944607&...

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    Code on Verilog and generate plots Завершено left

    Complete few tasks on Verilog software

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    Code on Verilog Завершено left

    Complete few tasks on Verilog software

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    7 ставки

    I have a map with coordinates (attached) I need a program that allows me to easily plot the location of accidents on this map. if i have a list of accidents, (say E1, A4, J7 etc) I need to be able to enter those coordinates and see them plotted on an online version of this map - (should be shows as a Red Dot or something that is small but visible) This needs to be highly interactive User Friend...

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    HW Help w/ Verilog & Vivado Завершено left

    Hey looking for some help with some introductory logic building using Verilog code on the vivado software. Also Its for basys3. It’s really elementary and if you know how to use vivado this should be quick and easy money for you. Thanks

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    Compile a verilog code Завершено left

    I need help in compiling a verilog code. I have already built a code that runs on a platform but when i run it on multisim, it gives me errors. I need an expert to guide me with this

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    Project for Chris H. Завершено left

    Hi Chris, I looked over your profile and believe you may be the perfect fit for one or multiple projects we have. We currently have a chat translation app that is written natively for iOS and Android, and also works in the browser. We would like to utilize the same backend API, which uses sockets and uses Nodejs. I also believe the database is using mysql, but I'm not entirely sure. This is s...

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    Simplistic Matrix engine Завершено left

    I want to create a simple CPU the do some mathematics logic between two matrices using Verilog code

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    Hi, I need to emulate a crystal oscillator circuit (attached) based on wave digital filter (WDF). Basically we aim to have WDF emulation that match a Spice simulation (e.g. in Cadence). I Already have the circuit simulated in Cadence (the output attached) . Attached, my circuit (Crystal Oscillator) schematic that needs to be mapped to WDF along with its output waveform, you will notice that there ...

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    Looking for designer Завершено left

    I am looking for designer to finish my logos and promotional images. He or She must have 3 years of experiences in design. Must be familiar with Adobe Photoshop, InVision, Principle, Framer ... Design sketches will be given in direct messages.

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    Magento 2 issues fix Завершено left

    E1. Registered users are not able to use the eway payment shows as invalid card but with guest users it is working. E2. Few design changes on the front end page, 1) the Logo should be increased 2) when the product is added to the Cart through mobile, the search and cart are getting overlapped and 3) remove the address from the contact us E3. During the registration, the mobile number validati...

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    I have a task on verilog and i want someone who is experience on it to help me with it. Please bid only if you know youre an expert. I will share details with interested freelancer. Budget is limited, hiring will be on a weekly basis

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    Hi, I need a basic example of a state machine in VERILOG. We need to find the pattern "100" using machine states. We have 4 states: S0: Initial state S1: If 1 is found S2: If 0 is found S3: If 0 is found Encoding: S0: 00 S1: 01 S2: 11 S3: 10 Transition: Actual state / Input / Next state 00 - 0 - 00 00 - 1 - 01 01 - 0 - 11 01 - 1 - 01 11 - 0 - 10 11 - 1 - 01 10 - 0 - 00 10 - 1 - 01 T...

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    I posted this a couple weeks ago but decided that the process was not in the direction I want to go for the future. I deleted the original post and welcome those that placed a bid to do it again. I am replacing my current E1 system that was developed to manage psychic calls, due to changes to the Telecommunications industry in Australia and am moving towards SIP service providers to meet my need...

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    Wanted Online FPGA Tutor Завершено left

    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

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    Existing Issues / Fixes Required: E1. During the registration, the mobile number validation should only be 04XXXXXXXX but not rest of the letters (048XXXXXXX consider as invalid phone number but it is actually valid phone number) E2. When customer selects the product and click on Cart, there is a Sign in option that displays on top side and it is observed that – the sign in from there is n...

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    FPGA Development Завершено left

    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

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    Embedded systems designers Завершено left

    Needs to hire 3 Freelancers We are a small and growing company offering consulting and engineering services in many different areas of industry. Here you can find more about us: [войдите, чтобы посмотреть URL] In order to enforce our team, we are seeking embedded systems designers with experience in the following domains: * PCB design (Altium Designer, Eagle, KiCAD, PCAD...) * Firmware design (C/...

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    Build a neural network Завершено left

    Hi, I need : * ANN IN FPGA using my mac unit? *zybo-zynq-7000-arm-fpga-soc-trainer-board/ *verilog *MNIST

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    8 bit processor Завершено left

    fix bug in verilog hdl for 8 bit

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    Design an 8-bit microprocessor using Verilog HDL by using Structural Verilog modelling. The individual components can be designed using behavioral modelling. Mandatory components: Instruction Memory Register File Data Memory ALU Control Unit Multiplexers Sign extend unit Program counter The Register File has two registers R0 and R1. Design the program counter and instruction memory such that input...

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