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    2,864 e1 framer vhdl работ(-а,-ы) найдено, цены указаны в USD

    необходимо создать городской портал по примеру [войдите, чтобы посмотреть URL] еще пример [войдите, чтобы посмотреть URL] в нем должны присутствовать следующие разделы: Новости(автоматически копирующие новости с популярных новостных сайтов ) Работа вакансии/резюме Авто покупка/продажа/статьи яндекс карты пробки Недвижимость купля/продажа Баннерная система (реклама) Справка (погода, курсы ...

    $1405 (Avg Bid)
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    Создание веб-сайта Завершено left

    необходимо создать городской портал по примеру [войдите, чтобы посмотреть URL] в нем должны присутствовать следующие разделы: Новости(автоматически копирующие новости с популярных новостных сайтов ) Работа вакансии/резюме Авто покупка/продажа/статьи яндекс карты пробки Недвижимость купля/продажа Баннерная система (реклама) Справка (погода, курсы валют, справочник предприятий города с карт...

    $304 (Avg Bid)
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    Переделка конвертера с С# на С/C++. Использование типовых пакетов linux. Работа с потоком E1/PRI, HDLC, LAPD, X25

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    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

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    Выписать в отдельную таблицу по полям Город, название, телефон, e-mail, сайт информацию об оптовых клиентах по городам России со следующих 6 сайтов. Пример таблицы во вложении. [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть URL]

    $150 (Avg Bid)
    Гарантированный
    Electronics design circuit 6 дней(-я) left
    ПОДТВЕРЖДЕН

    I have some design which are related to electronics. I want these digital design to be solved using vhdl. These task are pretty simple. i will provide you further details as you contact me

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    Job Description: We are looking for a UI/UX Designer who carries a passion for designing beautiful, intuitive experiences in complex, data-intensive web applications. Role & Responsibilities: • Solve complex interaction design problems and strive to create great customer experiences within our product offering. • Work across teams to create UI storyboards, wireframes, and concept d...

    $399 (Avg Bid)
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    Electronics Circuit 5 дней(-я) left

    I need some help which is related to digital design which to be solved using vhdl. These are simple tasks. As you contact i will provide you some details

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    i want to make some modifications in my site its a tv series and movies streaming [войдите, чтобы посмотреть URL] here is the modifications i want 1- Several Video players I can only add 1 video player so i want edit it so i can add more video players incase Player 1 is removed so visitors can watch via player 2 example: [войдите, чтобы посмотреть URL] this site use the same script as mine [во...

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    Project for Majid A. -- 2 8 дней(-я) left

    (1) FSM WITH VHDL+ TESTBENCH ( TRUTH TABLE,KMAP AND CODE)

    $56 (Avg Bid)
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    Build me an ALU using vhdl 4 дней(-я) left
    ПОДТВЕРЖДЕН

    Details will be provided upon in personal chat. Only experts apply, as I need product to be delivered asap.

    $194 (Avg Bid)
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    SITUATION: I have a VHDL design for a custom processor + peripherals that needs to go into an FPGA. It passes functional simulation that uses VHDL testbenches. I am in the process of adding VHDL checkers. This design needs to pass timing simulation with a (soft) target frequency of 50 MHz, be programmed into an FPGA, and be verified using an off-the-shelf FPGA card. While I'm strong in digit...

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    ALU design in VHDL 2 дней(-я) left

    mini arithmetic logic unit for signed and unsigned numbers

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    Arduino, FPGA expert 1 день left

    I have a Arduino sketch with Motor control. I want to change this code into VHDL or Verilog HDL. This is simple project. If anyone knows Arduino and FPGA, it takes one day to do it.

    $156 (Avg Bid)
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    VHDL Verilog 1 день left
    ПОДТВЕРЖДЕН

    Kann mir jemand helfen dieses Verilog Problem zu lösen?

    $38 (Avg Bid)
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    Project for Majid A. 3 дней(-я) left

    I have a VHDL+ TESTBENCH CODE. I want to create a small document. CODES AND MARKING SCHEME IS GIVEN THE DOC FILE.

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    Looking for a competent freelancer in FPGA, VHDL, Simulink and Python to do some work for me. Please read the attached document for full project specification

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    Restructuring and Code Conversion Завершено left

    I need parse Verilog (vhdl) code for fpga, structure the same code and rewrite to another fpga. The project is ready.

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    VHDL code of optimization algorithm fixing.

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    VHDL code of optimization algorithm fixing.

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    compiling email data in excel by visiting website – link given -tripur embroidery - dt 9-10-2019 Hi i will supply website link and would want company name , email id (different email ids in different columns) , contact name, contact no. in an excel to build up mailing list website link : [войдите, чтобы посмотреть URL] it has alphabetically organized company name and links to company...

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    clearly explain your datapath and control, and comment every single line of VHDL code

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    E1 Visa Help Needed Завершено left

    Hi, I was filling an E1 visa but there is one thing I need to fill that is DS-156E. "our employer must complete a DS-156E" I don't have an employer there. I do have a business here in my country and have an online website where I am getting orders from clients around the world but most 75% of my clients are from the US Let me know if there is anyone who can help me with this

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    This is basically a VHDL Programming to implement ALU for two 4-bit input numbers. I need the vhdl program, constraint files and the schematic logic design as well. Please reply me asap as i need it by this Tuesday morning. Thanks

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    office space and hotel Завершено left

    Taking an interdisciplinary approach, this project intends to reflects on the future of workplace and to consider the re-use of existing buildings and the creation of new relationships between public and private activities within an urban context. Create a mixed-use building - Primary Use: An office space accessible 24 hours a day to both the inhabitants of the building and the general public. -...

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    Photo composites Завершено left

    I'm a photographer with decent Photoshop abilities, but I think I recently bit off more than I can chew-- plus I'm under deadline pressure. The idea was to do a couple spoof images as a fun favor for a client whose husband has a 50th birthday approaching. His two favorite movies are Slapshot and (wait for it...) Xanadu. I photographed his wife and kids, in costume and lit, and I have a h...

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    Hi, PLEASE HEIP. I have a activity. It is design a 4-bit asynchronous up down counter using xilinx software. I want truth table, k maps and VHDL CODE + TEST BENCH. Specially i want 2 different VHDL + TEST BENCH But all answers must be the same. IDE DESIGN SUITE 14.2V

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    Do you have FPGA board? If yes I have a simple task to be done in FPGA with a sim,ple report. Interested freelancer is expected to use VHDL Language. Quartus V 17.0 will be better. Link will be provided Please bid only if you can work with Quartus and V17.0 to be prpecise. Its needed ASAP

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    6 ставки

    Do you have FPGA board? If yes I have a simple task to be done in FPGA with a sim,ple report. Interested freelancer is expected to use VHDL Language. Quartus V 17.0 will be better. Link will be provided Please bid only if you can do. Its needed ASAP

    $20 (Avg Bid)
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    3 ставки

    Do you have FPGA board? If yes I have a simple task to be done in FPGA with a sim,ple report. Interested freelancer is expected to use VHDL Language. Quartus V 17.0 will be better Please bid only if you can do. Its needed ASAP

    $13 (Avg Bid)
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    3 ставки

    Do you have FPGA board? If yes I have a simple task to be done in FPGA with a sim,ple report. Interested freelancer is expected to use VHDL Language Please bid only if you can do. Its needed ASAP

    $21 (Avg Bid)
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    6 ставки

    I need help building ASIC using bitmain chips. I will need the PSU, hashing boards, controller designed. Delivarables would be vHDL or verilog files, BOM, PCB layouts, etc. that would be required in producing the ASIC machine by giving such delivarables to PCB manufacturer.

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    Need some help adjusting a formula (P1) to work for cell E2. Right now P1 only works with E1

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    Part-Time Product Designer Завершено left

    I am looking US and east EU freelancers No bids (Asia) CartKit is seeking a Product Designer for 10-20 hours per week Join our small, passionate team on our mission to increase merchant sales through easy-as-pie marketing automation. Cartkit has helped over 125,000 Shopify stores recover more than $140,000,000 in sales. At CartKit, we believe that existing marketing tools are entirely too comple...

    $21 / hr (Avg Bid)
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    5 ставки
    VHDL/MATLAB Telecommunication Завершено left

    I need a MATLAB simmulink VDSL simulation to be completed. I am looking to see how distance will attenuate a VDSL signal. Can discuss more technical details.

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    Hello Team, We are facing issue in configuration of Sangoma (E1 PRI) card in Goautodial 3.0

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    Circuit Design Engineer Завершено left

    We are looking for a talented and driven hands on Electrical Engineer who will be part of creating an incredible cutting edge technology system. And will focus on the design, construction, and troubleshooting of compact and reliable embedded electrical systems . This includes electrical sub-system design, integration, PCB layout, and frequent hands-on work in lab building and debugging electrical ...

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    I am a product designer, and I need help with converting the design into a framer x prototype. The design is a desktop commerce web ui. I need help and especially for: 1. Creating the main search input and custom dropdown menus 2. Create the results page with filter dropdown and shopping items as cards 3. Can to change the results through the filters 4. Checkout page with input fields (name, ema...

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    I am using Altera DE2-115 FPGA board to configure it using Quartus software 17 lite edition. We have to use QSYS to assign addresses and link the processor, then assign inputs and outputs in VHDL and pin planner in Quartus, and then use NIOS II processor for Eclipse to write a program in C and run the board. I am seeking some help in building this mini thing. I am attaching a pdf file for the tas...

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    Looking for excel vba expert to help write a vba macro for following logic: Steps: Setting the period (first and last column where code should be executed) 1. First column = Today's date + E1 2. Last column = Today's date + F1 Push out logic 1. Match the AZs (E8:E24) to Gap/Excess (B63:B77) 2. For each matching AZs, if there is a excess (above 0, positive value) push the value in push/...

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    Crear VM con Issabel en VMware Завершено left

    Somos un call center argentino que trabaja con multicampaña. Necesitamos crear 3 VM (Maquinas virtuales) en un servidor Dell. En las 3 VM se deben instalar la versión mas reciente de Issabel (Central Telefónica). Debe esta bajo SO Linux. Parámetros: Configurar troncales y rutas salientes: Troncales: 1 Gateway synway GSM de 16 canales 1 Gateway Openvox GSM 12 canales...

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    Our company is seeking for a passionate UI/UX Freelancers who working directly with a multi-national team of accomplished software engineers in India, South Africa, Colombia, and the US. Our UI/UX Freelancers interact directly with other tech team members, as well as functional business managers and end users for the product around the globe. [Removed for encouraging offsite communication which is...

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    FIR filter Design using FPGA Завершено left

    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

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    I am currently using Altera DE2-115 FPGA board to configure it using Quartus 17 lite edition software and write the code in VHDL. We have to use QSYS, and NIOS II for Eclipse to write a program in C and to run the board. I am seeking some help in building this mini thing.

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    2 ставки
    FPGA DESIGN ENGINEER Завершено left

    We are seeking 1 FPGA Design Engineer for our new product development. FPGA Design Engineer Responsibilities: • Completing implementation in RTL • Ensuring robust and complete timing constraints • Optimizing FPGA code to balance performance, area, power, complexity and timing • Determining and executing development, integration, bring-up and test plans. • Working closely ...

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    Create some wireframes Завершено left

    I have a web application which serves as an internal tool for my company. I want a UI/UX designer to take a look at it and revamp the design of it by creating some wireframes using a tool like Sketch or Framer X.

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    GL algorithm Expert Завершено left

    hello, I am looking for expert who build GL algorithm using VHDL. If you can do it, we will discuss in details.

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