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    3,170 fpga altera работ(-а,-ы) найдено, цены указаны в USD

    Развести DDR3, топология FlyBy, 2 чипа Altera SoC. 8 слоев (S-P-P-S-S-P-P-S), для разводки DDR доступно 3 (4, 5, 8 слои). Допустимо изменение размещения компонентов, если критично. Правила по выравниванию и классы сигналов заданы. Срок до 28.02. Возможно расширение заказа до полной разводки платы с увеличением стоимости и расширением сроков.

    $250 (Avg Bid)
    $250 Ср. заявка
    1 заявок(-ки)
    Project for Pavlo H. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)
    Project for Mykyta M. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)
    $111 Ср. заявка
    1 заявок(-ки)

    Разработка системы Формирования звуковых оповещений на основе FPGA,(Development of a system for generating sound notifications based on FPGA.)

    $38 (Avg Bid)
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    3 заявок(-ки)

    Цветомузыка. Адресная светодиодная лента, фильтр по частотам (высокие, средние, низкие), в зависимости от громкости и частоты мигает лента разными цветами

    $17 (Avg Bid)
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    I am hiring Electrical & Electronics Engineers from PAKISTAN 6 дней(-я) left
    ПОДТВЕРЖДЕН

    Assalam o alaikum !!! I am hiring electrical engineers for working on my projects in following areas of electrical & electronics engineering: 1) FPGA (VHDL/Verilog) 2) Matlab 3) Multisim I have a lot of work in all the fields mentioned above. Its a big opportunity to work with us for long term basis. Even if you are a new freelancer, feel free to place your bid. I AM HIRING EXPERTS FROM PAKISTAN ONLY

    $73 (Avg Bid)
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    Send Automatic Whatsapp Message every sell ( my ERP have API ) 5 дней(-я) left
    ПОДТВЕРЖДЕН

    Hello. I have a sales system (ERP) that has an open API. I need and a BOT/System that whenever a sale happens, the bot sends a message to my client via whatsapp. System API is very complete. The API notifies you when there is a sale, the API has all the customer's data such as Phone number, Name, Address, emai...thank you message, with order information (information is available in the API) Bot need use my own mobile number... Invoice API: Order API: Callback Status order: ( portuguese, translate to your language )

    $201 (Avg Bid)
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    Basic calculator using vivado on basys3 fpga 2 дней(-я) left
    ПОДТВЕРЖДЕН

    To whom it may concern, I'm looking for someone experienced who can develop a basic calculator using verilog on vivado with specific requirements in a short period of time. If you think this fits your skills, let me know and lets discuss things further!

    $25 (Avg Bid)
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    I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit (DE10-Lite) and I need report about a project

    $37 (Avg Bid)
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    Dc motor pwm , vhdl using fpga 1 день left
    ПОДТВЕРЖДЕН

    I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite)

    $32 (Avg Bid)
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    5 заявок(-ки)
    FPGA Project 14 часов(-а) left

    1 Verilog/VHDL Programming language 2 Understanding of the protocol and standards 3 FPGA knowledge & Programming hands on 4 Knowledge of the safety standards. Optical Data link 5 Networking concepts

    $408 (Avg Bid)
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    11 заявок(-ки)

    I am using a 32x32 LED matrix from Adafruit and I am driving it with an FPGA. I followed the tutorial they provided and I get an image initialize. Now, I am trying to have various frames to show, to make some sort of video. I want to use a microcontroller to send the data for the frames to the FPGA. Further explanation is attached on the word document and all the files I currently am using will also be attached. Please don't hesitate to reach out with any questions regarding the design.

    $703 (Avg Bid)
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    Altera De1 SoC FPGA Завершено left

    Write a program using QUARTUS ALTERA to work on De1-SoC FPGA BOARD. .................. The LED Brightening Control with an Absolute Encoder The circuit to be designed must provide control of the brightness of a single or multiple LED ‘s using values from an Absolute Contacting Encoder (128 positions). In addition, the circuit must display a decimal value of the LED intensity (0-127) by using three seven-segment displays. The circuit contains four logic blocks and 3 external components (Figure 1). The logic circuits are: • Code Conversion Table • Binary to BCD 3 digits (Decimal Values) • LED Brightening Control (PWM) • Seven Segments Decoder

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    To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), m...are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), memory system, control unit etc. separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the ...

    $11 - $18 / hr
    Скрытый
    $11 - $18 / hr
    1 заявок(-ки)

    To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU)...considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), memory system, control unit etc. separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the <...

    $21 - $179
    Скрытый
    $21 - $179
    2 заявок(-ки)

    Title of the project HDL Digital Signal Processor core for FPGA implementation Deadline is in 15 hours budget is 20$ requirement for the scope will be through the chat Thanks

    $32 (Avg Bid)
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    FPGA Coder for Financial markets Завершено left

    I need someone to code me FPGA for financial markets

    $439 (Avg Bid)
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    10 заявок(-ки)
    Traffic Control System Завершено left

    Traffic Control System (Two intersection road) using VHDL in Quartus II. Write Code, test bench and simulate in Modelsim Altera. Draw Flow diagram or ASM chart and Mnemonic document state diagram.

    $30 (Avg Bid)
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    DSP Xilinx Zynq 2019.1 FPGA Завершено left

    This job consists of implementing into a Xilinx Zynq three pipelines into vivado 2019.1: A phase lock loop using fixed point A frequency lock loop A delay lock loop Timeline: 3 weeks

    $1233 (Avg Bid)
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    Car parking system counting from 0 to 99 in 7 segment using vhdl , fpga I have the code and testbensh but I have a problem when I click on the push buttons the 7 segment does not show the numbers Model of fpga kit=> (( rz easyfpga a2.2 ))

    $24 (Avg Bid)
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    Project for Islam M. Завершено left

    Hi Islam, I'm looking for somebody who can help me to implement blake2s protocol over a FPGA I have contacted you also on linkedin

    $11 (Avg Bid)
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    FPGA homework Завершено left

    i have a homework about fpga... i will inform about details when you message me

    $28 (Avg Bid)
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    11 заявок(-ки)

    Design Problem specification: To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such...considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), memory system, control unit etc. separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the

    $22 - $180
    Скрытый
    $22 - $180
    3 заявок(-ки)

    Implement an FPGA-BASED ADAPTIVE NOISE CANCELLING SYSTEM according to the first paper and provide a full report of the works done. After that study available solutions for binaural rendering and extend the previous experimentation to other rendering solutions according to the second paper with a full report

    $112 (Avg Bid)
    Гарантированный

    looking for an expert in FPGA programming who can help me to interface an ADC to an FPGA using Vivado design Suite. The connection between the ADC and the FPGA is via FMC connector. The FPGA board that i am using is a Nexys Video board which mounts an Artix-7 FPGA. I need to understand how trancievers work and how to use transceivers in order to connect the Nexys Video and the ADC. The model of the ADC is probably the AD9689.

    $149 (Avg Bid)
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    I developed a system that consists of 2 camera and 1 ethernet. The FPGA will get the image sensor data from 2 cameras and will process algorithm on the images. After processing, FPGA will send streaming data and processed data to the computer via Ethernet port. The protocol will be based on TCP/IP. I am looking for a long-term partner. I have many projects, so this will lead to other opportunities.

    $611 (Avg Bid)
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    9 заявок(-ки)
    Replicate an FPGA Завершено left

    Recreate an FPGA simulation based on an open-source project programmed onto an MCU and communicate with the FPGA via SPI. Logic Analyzer captures would be provided for reference.

    $623 (Avg Bid)
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    In this project I want to see how the ADC works in FPGA kit .. with any sensor LED or temp. The board is ALTERA Cyclone IV EP4CE6e22cb

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    Hi Ahmed M., I would like to discuss with you my project. I need your mentorship and guidance from an experienced guy like you to have my project done by myself, is this possible? We can discuss more details over the chat. Thanks, Omar

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    ethhash bitstream Завершено left

    i have Xilinx FPGA BCU/VCU1525 Card, i want to bit Stream for Ethereum Coin, and i have also vivado lab 2020,

    $2650 (Avg Bid)
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    Modify a existing controller on a FPGA (Cyclone III), which is used to calibrate the coefficients of a filter on another demo board. Already have a prototype, but needs to run modelsim and to modify existing verilog codes. Need someone who has a strong background with Quartus and FPGA design. Thank you.

    $191 (Avg Bid)
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    VHDL/Quartus Expert from Pakistan Завершено left

    ...separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the FPGA board. The documentation should show justification for any design decisions that you make as well as development logs for both hardware and software. Evidence of approaches used for the codesign, co-implementation, co-testing, co-integration, and system integration must be provided. This assignment will provide experience of the problems and decisions in developing co-design projects. There are many possible solutions to the design problems depending on the way in which you choose to partition each problem. HW/SW Specs: The target embedded systems platform can be either the AlteraDE0 FPGA...

    $22 - $182
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    ı need help for microprocessor design who know assembly, Logisim ,Verilog and knowlage about FPGA

    $133 (Avg Bid)
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    Need an FPGA expert Завершено left

    Need an FPGA expert with proficiency in VHDL

    $130 (Avg Bid)
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    Need to work on VIVADO and be able to code on VHDL and implement it on a FPGA board.

    $140 (Avg Bid)
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    2 заявок(-ки)
    Vhdl fpga alarm clock nexys4 ddr Завершено left

    I want to build alarm clock using vhdl in nexys4 ddr fpga board. Display clock in 7 segment display. Modify hour and minutes and set alarm and if possible set stopwatch. Not verilog. Using vhdl.

    $45 (Avg Bid)
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    Vhdl program to display digital clock using nexys 4 ddr in vga display. Vhdl not verilog. Using xilinx vivado

    $50 (Avg Bid)
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    Digital Electronics Project Завершено left

    Looking for a freelancer to implement an FPGA project.

    $147 (Avg Bid)
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    8 заявок(-ки)

    Verilog Expert needed with good hand's on FPGA

    $17 (Avg Bid)
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    HDMI mix engine Завершено left

    Mixing 2 HDMI inputs with FADE control to one HDMI output (FPGA or ARM) need to suggest hardware platform and discuss how it will be implemented before the project will be awarded. Only apply if you have done such a project previously or have good FPGA programming abilities.

    $2384 (Avg Bid)
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    I need help to Implement the Snakes and Ladder game on NEXYS 4 DDR FPGA with the help of the VHDL. I will provide more details in chat

    $66 (Avg Bid)
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    6 заявок(-ки)

    ...project is to implement a GPS / Galileo signal tracking algorithm into the FPGA side of a Zynq 7020. A first algorithm has been already developed and validiated on Matlab. The scope of this job is Task-1.1 FPGA Design to convert the GNSS tracking algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-1.2 Validation of the VHDL design using 3D Aerospace pre-recording data on Zedboard Task-1.3(optional) Development of a Petalinux application for real-time implementation (v2019.1) Task-1.4 Provide a clean code with the associated documentation. Task-2.1 FPGA Design to convert the GNSS demodulation algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 usi...

    $21 / hr (Avg Bid)
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    4 заявок(-ки)

    The broad area regarding the project is related to fingerprint identification and classification using CNN algorithm which is to be implemented using simulink on FPGA board

    $444 (Avg Bid)
    $444 Ср. заявка
    3 заявок(-ки)

    ...project is to implement a GPS / Galileo signal tracking algorithm into the FPGA side of a Zynq 7020. A first algorithm has been already developed and validiated on Matlab. The scope of this job is Task-1.1 FPGA Design to convert the GNSS tracking algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-1.2 Validation of the VHDL design using 3D Aerospace pre-recording data on Zedboard Task-1.3(optional) Development of a Petalinux application for real-time implementation (v2019.1) Task-1.4 Provide a clean code with the associated documentation. Task-2.1 FPGA Design to convert the GNSS demodulation algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 usi...

    $32 / hr (Avg Bid)
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    4 заявок(-ки)
    FPGA Mining Завершено left

    FPGA Mining fot Xilinx® Alveo™ U30

    $116 (Avg Bid)
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    3 заявок(-ки)
    Project for Fernando Andres G. Завершено left

    Hi Fernando Andres G., I noticed you worked on a project to mine ETH in the past on the FPGA (xilinx board), did you manage to port the whole algorithm in there? In case it's true, can you tell me what FPGA cards you managed to port this algo?

    $90 (Avg Bid)
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    1 заявок(-ки)
    LiDAR DNN Review for FPGA. Завершено left

    Hi Islam M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $10 (Avg Bid)
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    Build a LMS adaptive FIR Filter Завершено left

    Implementation of Adaptive Filter for echo cancellation using FPGA and verilog.

    $59 / hr (Avg Bid)
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    7 заявок(-ки)