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    3,427 fpga spartan verilog projects работ(-а,-ы) найдено, цены указаны в USD

    ...эти материалы. 3. Сайт должен уметь обрабатывать флэш 4. Сайт должен уметь нормально отображаться в разных версиях основных браузеров: Mozilla Firefox, Internet Explorer, Spartan, Safari, Opera 5. Сайт должен выдерживать нагрузку в 100 тысяч посещений в день. 6. Сайт должен иметь личный кабинет. Должна быть форма регистрации. 7. Сайт должен содержать

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    Need an implementation of a TDC on the Artix-7 for a LIDAR application. Should work on Digilent Cmod-7 Board for hardware testing. Higher pay for higher resolution. Inports: clk (144MHz) rst (active low) startstop (after reset, first rising edge is start signal, second rising edge is stop signal) Outports: data ready (active high) dataout (16bits) Should reset every time a reading is needed, a...

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    ...of arbitrary size over ethernet and zedboard FPGA should receive and do a logic operation on data and send back a packet of a different size back to the PC. Design also requires interfacing with the PHY chip on zedboard. Important note, your implementation should ONLY use PL part of the fpga and no FPGA specific units (like cpu cores, AXI bus, HARD

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    Project for totori1990 8 дней(-я) left

    Hi totori1990,I found that you applied for the project of developing fpga application on Solarflare AOE SFA7942Q device which is titled as "Freelance FPGA engineer". I'm considering a similar project. If you took that project, I want to ask you more details about the result.

    $2000 (Avg Bid)
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    in matlab design on adaptive fir filter design and implementation on FPGA this is mtech project

    $333 (Avg Bid)
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    Project for Gurbir P. 7 дней(-я) left

    sir my project is fir filter design and implementation on FPGA VLSI .

    $144 (Avg Bid)
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    Project for Hammad M. 7 дней(-я) left

    hello sir I want to make Adaptive fir filter design simulation and implementation on FPGA project mtech sir

    $144 (Avg Bid)
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    Need to develop a very simple game using VHDL, to be run on an Altera DE1-SoC FPGA board. The game will use as external 4x4 keypad which will be connected to the board via one of the GPIO ports on the board. Also the game will use some 7-segment displays on the board to display some information regarding the game. The game itself is quite simple and

    $354 (Avg Bid)
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    Modify cgminer or bfgminer driver file so it will work with FPGA mining hardware connected with USB-UART bridge. Bitstream is programmed on the SPI ROM in the FPGA miner. Mining bitcoin, and need to be connected to pool that works on stratum (supported with cgminer/bfgminer)

    $195 (Avg Bid)
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    We have existing hardware based on Xilinx XC7K160T-2FFG676 and TI DAC5682ZIRGC25 We want a verilog interface that accepts 32bit axi stream and is capable of speeds in excess of 400Msps. If needed, the internal interface can be 64bit axi stream on half the sample rate, but the external data rate to the DAC must be 400MSps or higher. A 2nd module

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    FPGA IMPLEMENTATION VHDL CODE USING ALGORITHMS OF GA, AND CONTROL UNIT SYSTEM

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    I have 1.25 Mbps data on an avalon-ST interface to be transferred to the HPS then to the ethernet port on DE1-SOC board. The data are on 24 channels of 24bit samples. I need you to explain the work to me in case I need to modify it or change the platform. My project which collects the data is attached. The top-level file is i2s_dsp

    $42 / hr (Avg Bid)
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    FPGA simple circuit board design 1 день left
    ПОДТВЕРЖДЕН

    Circuit board designer required for FPGA board with the following specifications. PCI-Express Xilinx Kintex 7 FPGA 50a VCCINT power to FPGA JTAG port (Possible option of 2 x DDR3 SODIMM RAM Slots)

    $2073 (Avg Bid)
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    Image processing using verilog 20 часов(-а) left

    I want to do image processing for some of my images its basically a red color segmentation from the image and detect the patterns using verilog..... the image size is 240x240

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    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

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    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

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    I am currently working on some small project need to implement an image processing on FPGA, which may include patterns detection after red color segmentation and recognizing the detected patterns....the image size is 240x240 which has some patterns covered in red color

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    This project need to ...buffer This project is completed after simulating transfer (Buffer content ==> FPGA RAM content) This is the testing project, so that, you can get more projects after completing this. If you have experiences, you can complete within a few days. Deliverables: Verilog & buffer frame communication simulation in Xilinx Vivado

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    The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC. As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.

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    I have a de1-soc fpga board ([войдите, чтобы посмотреть URL]) for the detail. currently i have difficulty id generating code for image processing for my image. I have a completed matlab code that include the image and filtering kernel. I need the code to run into my fpga board.

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    Project for olegkaravaev84 Завершено left

    Hi olegkaravaev84, I noticed your profile and would like to offer you my SystemVerilog/Verilog FP{GA project. We can discuss any details over chat.

    $450 / hr (Avg Bid)
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    We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.

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    FPGA and Verilog Expert Завершено left

    an expert on FPGA and Verilog should bid only...

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    Create a Logo Завершено left

    Create a logo with a muscular spartan warrior holding a M2 machine gun in a similar fashion to the example attached. I would like the logistics crest some how implemented either as a background or as a tattoo on his arm. Also a laurel wreath to frame the design. I would like to use red, gold, blacks, greys, and whites for this design.

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    Verilog Design Завершено left

    I have one architecture, needs the RTL verilog code for the design to be made and followed by placement and routing to derive the power.

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    1. Vivado HLS fixed code optimization 2. Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HL... Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HLS 5. Intergration of IP generated in HLS in Verilog code

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    ...to this site [войдите, чтобы посмотреть URL] but with only Category A and B. Only minimal changes in terms of colors n looks, just to avoid copy write breaches. Want to keep it as spartan as the app itself. The information for the 40 random questions for Category A, the 45 random questions for Category B could be found here [войдите, чтобы посмотреть URL]

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    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design

    $104 (Avg Bid)
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    7 ставки

    Using Altera DE1-SoC FPGA board, I want you to write a code which can do FFT of the provided signal using Quartus II and Modelsim.

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    Trophy icon Living Greater Health OFA Free Offer Завершено left

    ...their kids and spouse and are ready to stop letting "life" get in the way of living. My ideal client has competed or wants to compete in an obstacle course event such as a Spartan or Tough Mudder, Ironman etc, they mountain bike, ski, hike, run, and are driven to try new things and want to have the fitness to be able to say yes to life's adventure.

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    Гарантированный

    ...(c-9896) to drew the black white picture on paper First, get the picture and manipulate it to make black and white Second, convert the picture to hex decimal and upload it to fpga ( nexys 4 ddr) using matlab Third, control the robot arm to get the pen and drew the picture. the expectation of the project is to have the following: - the required codes

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    The brightness measurement with help of PMODALS sensor ([войдите, чтобы посмотреть URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([войдите, чтобы посмотреть URL]) is to be used, which takes over the control. The

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    Project for Jin C. Завершено left

    Hi Jin, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $160 (Avg Bid)
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    1 ставки
    Project for Ahmed M. -- 2 Завершено left

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $200 (Avg Bid)
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    1 ставки
    Project for Ahmed M. Завершено left

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $160 (Avg Bid)
    $160 Ср. ставка
    1 ставки
    FPGA Project 2xI2S to SPI MCU Завершено left

    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

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    This is a long term project to teach and train a software engineer about advanced Electronics, PCB design and FPGA programming. This needs between 3 and 5 hours of face to face (online video conferencing) each week and excellent communication in English. So the payments are weekly as we have the online conferecing calls. The details of what will be

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    Trophy icon Engineer consultant Business Card Завершено left

    ...have any logo, a simple one is appreciated or also a simple standard design that represent my work is enough (google image keyword: circuit, pcb, electronic design, firmware, fpga, power electronics ) I would like to have a list of skills that I have on the business card, they are: Power Electronics, Hardware Design, Firmware, Digital Control, Altium

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    Гарантированный

    I want to implement YoloV2/V3 custom object detection on FPGA. I have my trained yolo custom object detection files(.cfg and .weights) using darknet and now i want to implement yolo using this files on Xilinx FPGA. I am using ZCU102 and PYNQ evaluation boards with me.

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    FPGA IP Development Завершено left

    I need some IPs(PHY/MAC...) for digital communication systems.

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    I Need Programmer Завершено left

    I Need Programmer For FPGA Board & Software Development.

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    build mac unit Завершено left

    build mac unit using verilog language. I have already done the multypler part and I need help to build the rest

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    1- I need someone to design a fully-digital, hardware-based keyboard encoder for a 16-key (4×4) matrix keyboard. 2- The design is to be implemented using an FPGA and verified by both simulation and physical implementation using a development board. 3- You should have Development boards, design software and encoder hardware 4- Separate documents will

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    verilog skills required Завершено left

    Basically I would like to have the verilog coding to build on my basys3 hardware. required to control the LED with left and right pushbutton within a range, to code different frequency for the LED within that range, to code one letter on each 7segment and the speed of the letter being displayed is depend on the frequency coded to the led. to code a

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    ...explaining different aspects of that algorithm. - Explain FPGA developers about Blockchain, cryptocurrency, how crypto-mining works. How to mine that particular algorithm. - Work with them and help them understand how crypto-mining works. And how to mine that perticular algorithm. - Support FPGA developers throughout development. - Must be fluent in

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    FPGA mining hardware - Xiling FPGA - Nexys Video - Can be leveraged from open source bitcoin miner code. - Based on Verilog. - Provide source code, constraints and full recipe for synthesis, implementation and bitstream generation - Connectivity via JTAG to the host (via USB). May consider UART instead, but as a less desirable solution. Mining software:

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    design with Altera FPGA Завершено left

    I have a VHDL source for the Altera EP3C25F256C8 FPGA design. I like an expert to setup the timing and fitting parameters to give the design optimum performance. I use Quartus II software version 8.1

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