Фильтр

Мои последние поисковые запросы
Фильтровать по:
Бюджет
по
по
по
Тип
Навыки
Языки
    Статус работы
    5,649 fpga verilog vhdl работ(-а,-ы) найдено, цены указаны в USD
    Project for Pavlo H. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)
    Project for Mykyta M. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)

    Имеется проект VHDL, необходимо процессы вынести в отдельные компоненты без потери функциональности и работоспособности тестбенча.

    $35 (Avg Bid)
    $35 Ср. заявка
    1 заявок(-ки)
    $111 Ср. заявка
    1 заявок(-ки)

    Разработка системы Формирования звуковых оповещений на основе FPGA,(Development of a system for generating sound notifications based on FPGA.)

    $38 (Avg Bid)
    $38 Ср. заявка
    3 заявок(-ки)
    Project for Sergey G. Завершено left

    Здравствуйте, Sergey G.! Я обратил внимание на ваш профиль и хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $35 (Avg Bid)
    $35 Ср. заявка
    1 заявок(-ки)
    Project for Oleksandr S. Завершено left

    Здравствуйте, Clevermindolex! Хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $30 (Avg Bid)
    $30 Ср. заявка
    1 заявок(-ки)

    Цветомузыка. Адресная светодиодная лента, фильтр по частотам (высокие, средние, низкие), в зависимости от громкости и частоты мигает лента разными цветами

    $17 (Avg Bid)
    $17 Ср. заявка
    1 заявок(-ки)

    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

    $23 (Avg Bid)
    $23 Ср. заявка
    4 заявок(-ки)
    vivado xilinx expert needed 6 дней(-я) left
    ПОДТВЕРЖДЕН

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $184 (Avg Bid)
    $184 Ср. заявка
    1 заявок(-ки)
    Testbench in VHDL 6 дней(-я) left

    I have a source code and I want the testbench code for it

    $47 (Avg Bid)
    $47 Ср. заявка
    2 заявок(-ки)
    need help in verilog stuff 6 дней(-я) left

    i need some help which is related to verilog structure coding

    $16 (Avg Bid)
    $16 Ср. заявка
    3 заявок(-ки)
    Verilog Alarm Clock 6 дней(-я) left
    ПОДТВЕРЖДЕН

    Design the control logic for an alarm clock (for simulation purposes 20ns simulation = 1 minute real time –this can be adjusted somewhat for simulation purposes). a) Use multiple input signals (alarm set input, the snooze, and the alarm time). b) The design will contain one output (Alarm_On). A logic high at the output represents the alarm being “on”. c) An input will be used ...

    $82 (Avg Bid)
    $82 Ср. заявка
    6 заявок(-ки)
    vivado expert needed -- 2 6 дней(-я) left
    ПОДТВЕРЖДЕН

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $7 (Avg Bid)
    $7 Ср. заявка
    1 заявок(-ки)
    vivado expert needed 6 дней(-я) left
    ПОДТВЕРЖДЕН

    i want long term employee. if you are expert in verilog, vhdl. please bid here

    $4 / hr (Avg Bid)
    $4 / hr Ср. заявка
    2 заявок(-ки)
    Vhdl project -- 4 6 дней(-я) left
    ПОДТВЕРЖДЕН

    I need some clarification on vhdl

    $112 (Avg Bid)
    $112 Ср. заявка
    11 заявок(-ки)
    need help with vhdl 5 дней(-я) left

    Vending Machine Purpose: To use different acquired logic designs To gain experience of team work To design a VHDL based soda machine To test the design on the [войдите, чтобы посмотреть URL] site Tools: Compiler and testbench tools on [войдите, чтобы посмотреть URL]

    $21 (Avg Bid)
    $21 Ср. заявка
    3 заявок(-ки)
    Need an expert in Verilog 5 дней(-я) left

    Need an expert in Verilog . Need to familiar designing lowest possible latency systems

    $19 (Avg Bid)
    $19 Ср. заявка
    1 заявок(-ки)
    Verilog work 5 дней(-я) left

    Need someone who is fluent with Verilog code. A simple hexadecimal calculator will have to be coded. Need it done quick.

    $22 (Avg Bid)
    $22 Ср. заявка
    3 заявок(-ки)
    Digital Electronics 5 дней(-я) left
    ПОДТВЕРЖДЕН

    CMOS logic gates, digital circuit design using Verilog HDL and logic synthesis, clock distribution, digital circuit implementations and verification, digital memory and signalling technologies.

    $79 (Avg Bid)
    $79 Ср. заявка
    11 заявок(-ки)
    FPGA Design Project 5 дней(-я) left

    Please see attached pdf file to get complete details related to this task. This required template has been added in zip file.....

    $87 (Avg Bid)
    $87 Ср. заявка
    7 заявок(-ки)

    Looking for Linux Kernel developers And FPGA developers to port the Mister Project Linux Kernel and U-Boot of DE10 Nano to the Xilinix Ultra96-V2 Zynq UltraScale+ ZU3EG. Once completed we need assistance porting of the existing FPGA cores of Mister Project to the zu3. Mister Project Linux Kernel: [войдите, чтобы посмотреть URL] Mister Project U-Boot: [войдите, чтобы посмотреть URL] [войдите, ...

    $548 (Avg Bid)
    $548 Ср. заявка
    5 заявок(-ки)
    Need A VHDL expert for a small theory task 4 дней(-я) left
    ПОДТВЕРЖДЕН

    You have a VHDL code and you need to describe it. I would provide example

    $17 (Avg Bid)
    $17 Ср. заявка
    7 заявок(-ки)

    Looking for Linux developers And FPGA developers to port the Mister Project Linux Kernel of DE10 Nano to the Xilinix Ultra96-V2 Zynq UltraScale+ ZU3EG. Once completed we need porting of Current developed D10 Nano cores to the zu3.

    $583 (Avg Bid)
    $583 Ср. заявка
    3 заявок(-ки)

    I need the help of someone who could help me propose and implement an algorithm using constraints programming methods that supports formal verification of digital models that can be used on hardware models in VHDL , verilog, e.t.c, its quite urgent please, your help would be highly appreciated

    $131 (Avg Bid)
    $131 Ср. заявка
    7 заявок(-ки)

    Hi, this project will require you to use verilog and basys3 board and logic analyzer to do the work. Contact me if you are an expert in this.

    $56 (Avg Bid)
    $56 Ср. заявка
    4 заявок(-ки)
    Project for Muhammad B. 6 дней(-я) left

    Hi binyameen i have lab report in vhdl can you work in it

    $10 (Avg Bid)
    $10 Ср. заявка
    1 заявок(-ки)
    Project for Muhammad A. 6 дней(-я) left

    Hi Muhammad A., i have lab report in quartus vhdl can you work in it.

    $10 (Avg Bid)
    $10 Ср. заявка
    1 заявок(-ки)

    The booth multiplier circuit is from a research paper. I will give you the research paper.

    $20 (Avg Bid)
    $20 Ср. заявка
    5 заявок(-ки)
    design and verification 2 дней(-я) left
    ПОДТВЕРЖДЕН

    design of an FPGA device and its verification

    $119 (Avg Bid)
    $119 Ср. заявка
    15 заявок(-ки)
    Verilog coding on FPGA's 1 день left
    ПОДТВЕРЖДЕН

    I need an expert who can do implement modular multiplication algorithms in Verilog and simulate their results to make a comparison in their speed of implementation, hardware consumed etc.

    $336 (Avg Bid)
    $336 Ср. заявка
    19 заявок(-ки)

    I'm required to design this architecture using VHDL. This architecture also consists of hops.

    $110 (Avg Bid)
    $110 Ср. заявка
    8 заявок(-ки)

    We have a HW card already built that captures data and stores it inside the LSRAM of Microsemi Polarfire FPGA. We use double buffering technique so while capturing new data in one buffer the other buffer is sending the data to the host from the other buffer. The host has to capture the data in real time. For that, the Host PCIE has to allocate multiple buffers (e.g. cyclic Fifo) so the copied da...

    $2562 (Avg Bid)
    $2562 Ср. заявка
    4 заявок(-ки)

    It is an easy project message me for details

    $142 (Avg Bid)
    $142 Ср. заявка
    9 заявок(-ки)
    Robotic Expert 9 часов(-а) left
    ПОДТВЕРЖДЕН

    Hello freelancers, I am looking for an expert in VHDL/FPGA for an interesting project. The project is very small and I encourage new freelancers to place the bid. My budget is 30-40 AUD

    $82 (Avg Bid)
    $82 Ср. заявка
    4 заявок(-ки)
    VHDL Expertss 9 часов(-а) left
    ПОДТВЕРЖДЕН

    Hello freelancers, I am looking for an expert in VHDL for an interesting project. The project is very small and I encourage new freelancers to place the bid. My budget is 30-40 AUD

    $43 (Avg Bid)
    $43 Ср. заявка
    6 заявок(-ки)
    verilog, vhdl expert needed -- 3 6 часов(-а) left
    ПОДТВЕРЖДЕН

    i want long term employee. i need to draw internal block diagram. if you are expert, please bid here

    $3 / hr (Avg Bid)
    $3 / hr Ср. заявка
    7 заявок(-ки)
    verilog, vhdl expert needed -- 2 4 часов(-а) left
    ПОДТВЕРЖДЕН

    i want long term employee. i need to draw internal block diagram. if you are expert, please bid here

    $2 / hr (Avg Bid)
    $2 / hr Ср. заявка
    6 заявок(-ки)
    Verilog expert needed 3 часов(-а) left

    contact me to know about the project

    $29 (Avg Bid)
    $29 Ср. заявка
    7 заявок(-ки)
    verilog, vhdl expert needed 3 часов(-а) left
    ПОДТВЕРЖДЕН

    i want long term employee. i need to draw internal block diagram. if you are expert, please bid here

    $40 (Avg Bid)
    $40 Ср. заявка
    2 заявок(-ки)
    Looking senior Verilog engineers Завершено left

    - Develop a micro-threaded RISC-V for low-overhead threading - Integrate with FPGA HLS tool to make a solution of micro-threaded HLS - Need to optimized PPA (Power Performance Area) - Require good problem solving skill - Require good written and oral communication kill

    $7297 (Avg Bid)
    $7297 Ср. заявка
    3 заявок(-ки)

    1. Encode key presses on a standard 16-key 2. give a stable 4-bit binary output 3. Have output to indicate when a key is being pressed.

    $142 (Avg Bid)
    $142 Ср. заявка
    8 заявок(-ки)
    Robotic Expert (VHDL) Завершено left

    Hello freelancers, I am looking for an expert in VHDL for an interesting project.

    $173 (Avg Bid)
    $173 Ср. заявка
    6 заявок(-ки)

    This project has multiple phase that need to be done. It is yo develop a system that demonstrate the error correction H(7,4) hamming codes Use of python, Verilog and arudino is also required

    $40 - $67
    $40 - $67
    0 заявок(-ки)
    CME HFT FPGA tick to trade -- 2 Завершено left

    I'm a trader and I need an HPGA engineer foran ultra low latency fpga solution to trade on CME. I have a c++ reference implementation for most blocks, obviously this needs to be converted to hdL (verilog ideally). Functional requirements: - Msrket Data feed handler - Order book building (Last bid, ask, trade) - Line arbitration (Feed A and B arbitration) - orders sending - Exchange orders re...

    $10000 (Avg Bid)
    $10000 Ср. заявка
    2 заявок(-ки)
    $18 Ср. заявка
    6 заявок(-ки)
    Looking for verilog expert Завершено left

    I need help with a Verilog Project, using the Vivado software and a Basys 3 board.

    $26 (Avg Bid)
    $26 Ср. заявка
    7 заявок(-ки)
    CME HFT FPGA tick to trade Завершено left

    I'm a trader and I need an HPGA engineer foran ultra low latency fpga solution to trade on CME. I have a c++ reference implementation for most blocks, obviously this needs to be converted to hdL (verilog ideally). Functional requirements: - Msrket Data feed handler - Order book building (Last bid, ask, trade) - Line arbitration (Feed A and B arbitration) - orders sending - Exchange orders re...

    $3000 - $5000
    $3000 - $5000
    0 заявок(-ки)

    I need an expert who has knowledge of verilog vivado and is confident enough to work/ simulate the results and make a comparison.

    $149 (Avg Bid)
    $149 Ср. заявка
    2 заявок(-ки)