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    4,448 fpga vhdl verilog работ(-а,-ы) найдено, цены указаны в USD

    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

    $23 (Avg Bid)
    $23 Ср. ставка
    4 ставки
    Custom Camera Software 6 дней(-я) left

    We plan to use the Sny IMX420 imager, the Framos IP Core and a Xilinx FPGA. Looking for a vision software freelancer with experience in these technologies. Vivado 2018 or later.

    $50 / hr (Avg Bid)
    $50 / hr Ср. ставка
    3 ставки
    Digital Systems 6 дней(-я) left

    I need a help with VHDL Design. Please reply me if you can help me with this. afte that i will share more details

    $30 (Avg Bid)
    $30 Ср. ставка
    2 ставки
    Simulating Multiple Gates - Third installment (Verilog + C) 6 дней(-я) left
    ПОДТВЕРЖДЕН

    The first installment of the project dealt with the capability to simulate the actions of four very simple gate types, an INV gate, an AND gate, an OR gate and an XOR (exclusive or) gate. The second installment extended that capability by describing the simple logic gates using Verilog, but the Verilog was restricted to descriptions of circuits which only contained a single gate. For the third ins...

    $66 (Avg Bid)
    $66 Ср. ставка
    8 ставки
    Project in system verilog 6 дней(-я) left
    ПОДТВЕРЖДЕН

    Build a project using system verilog

    $198 (Avg Bid)
    $198 Ср. ставка
    10 ставки
    CSE/EEE Micro-controller Application 5 дней(-я) left
    ПОДТВЕРЖДЕН

    Micro-controoler Application on Terasic DE10-Lite, FPGA board

    $40 (Avg Bid)
    $40 Ср. ставка
    3 ставки
    Work on VHDL Laboratory like Latches, Flip-flops and registers 4 дней(-я) left
    ПОДТВЕРЖДЕН

    Need to investigate the latches, flip-flops and the registers in VHDL laboratory work

    $76 (Avg Bid)
    $76 Ср. ставка
    7 ставки
    FPGA U96 speed test 4 дней(-я) left

    Carry out simple speed test for development board Xilinx U96. Target price is 50 €.

    $114 (Avg Bid)
    $114 Ср. ставка
    7 ставки

    I want to hire a person who has an experience in solving problems related to verilog in VLSI design(small work though),has to be experienced in handy usage of software like xilinx/[войдите, чтобы посмотреть URL] for the problem and other info.

    $21 (Avg Bid)
    $21 Ср. ставка
    5 ставки

    (2) Random Examples must be created using System Verilog. The Examplesmust be simulated (Model Sim) and synthesized (SynplifyPro). Example figures attached. Results should be attached as a jpg or pdf.

    $25 (Avg Bid)
    $25 Ср. ставка
    4 ставки
    Project for Ankita L. -- 2 7 дней(-я) left

    it a vhdl coding project I want it in 3 days max.

    $45 (Avg Bid)
    $45 Ср. ставка
    1 ставки

    digital Alarm clock. I need it for my final project. Please let me know if anyone can do it in 20$. Lowest bit will be rewarded.

    $61 (Avg Bid)
    $61 Ср. ставка
    9 ставки

    This Project is to investigate latches, flip-flops and registers. VHDL -- Quartus Prime Lite 18.1 Quartus. design simple processor

    $20 (Avg Bid)
    $20 Ср. ставка
    2 ставки

    This Project is to investigate latches, flip-flops and registers. VHDL -- Quartus Prime Lite 18.1 Quartus.

    $15 (Avg Bid)
    $15 Ср. ставка
    2 ставки

    Budget: $20-$30 CAD Timeline: 24-48 hours Please see attached doc for more details.

    $30 (Avg Bid)
    $30 Ср. ставка
    2 ставки
    Simulating Multiple Gates third installment c + verilog 3 дней(-я) left
    ПОДТВЕРЖДЕН

    The first installment of the project dealt with the capability to simulate the actions of four very simple gate types, an INV gate, an AND gate, an OR gate and an XOR (exclusive or) gate. The second installment extended that capability by describing the simple logic gates using Verilog, but the Verilog was restricted to descriptions of circuits which only contained a single gate. For the third ins...

    $50 (Avg Bid)
    $50 Ср. ставка
    16 ставки
    OFDM Waveform Development 3 дней(-я) left
    ПОДТВЕРЖДЕН

    Need someone to develop OFDM waveform on AD9361 or any other transceiver and FPGA.

    $1195 (Avg Bid)
    $1195 Ср. ставка
    9 ставки
    Digital Logic Project 3 дней(-я) left

    hello, please if you can comment out the verilog code and the steps done, so we know how to explain it. also, i need this project to be done in exactly one week from today. thank you

    $49 (Avg Bid)
    $49 Ср. ставка
    7 ставки
    electric engineering 18 часов(-а) left

    Need someone know well vhdl ............................. ............................. .............................

    $31 (Avg Bid)
    $31 Ср. ставка
    13 ставки
    FPGA Implementation Завершено left

    FPGA Implementation of a 4-bit look-ahead carry adder - need to code in VHDL. BUDGET IS 20 CAD.

    $17 (Avg Bid)
    $17 Ср. ставка
    4 ставки
    Project for Vinod L. 1 день left

    Hi vinodluhar, I noticed your profile and would like to offer you my project. We can discuss any details over email. The project is the same as in this link: https://www.freelancer.com.bd/projects/fpga/embedded/

    $100 (Avg Bid)
    $100 Ср. ставка
    1 ставки
    FPGA OpenCL implementation Завершено left

    I have an application that I want to run on, Field programmable array gates (FPGAs) architecture using the parallel programming language OpenCL. The software and the FPGAs board I am using are from Xilinx company. The OpenCL compiler is Xilinx SDSoC OpneCL. I need help with optimising the code using the OpenCL and FPGAs methods to run the code faster. I have already tried that but I am not happy ...

    $221 (Avg Bid)
    $221 Ср. ставка
    6 ставки
    Write code for Embedded project Завершено left

    It is to develop a waveform viewer (WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports three analog channels, with a single-level triggering. Only 8 bits of precision will be used for each analog channel

    $99 (Avg Bid)
    $99 Ср. ставка
    7 ставки

    All code written in system verilog and the functions mod or divide not allowed Time should be displayed on the 6 digits of the seven segment displays (HHMMSS) -hours displayed in military time -when SW2=1, alarm is set and 6 digits display alarm time -when KEY0=0, the alarm is reset to 0, KEY0 takes priority over SW2 The alarm clock must be accurate, divide down the 50MHz clock at PIN_P11 as neces...

    $255 (Avg Bid)
    $255 Ср. ставка
    10 ставки

    I will provide you with a list of 15 very basic questions about the VHDL language for FPGAs. I need you to answer them with a minimum of 100-200 words for each answer. Your answers will be put into a spreadsheet. Your answers need to have great spelling, grammar, and be 100% unique. I don't want any copy/paste answers, and I will be checking for duplicate content. This is an introductory j...

    $95 (Avg Bid)
    $95 Ср. ставка
    8 ставки
    Neural network using Verilog -- 2 Завершено left

    I have a verilog project in which i have to implement neural network to recognize Amazon packages from the given binary matrix image. I already made most of the design code. I am new to verilog and need to finish the project till the final layout.

    $55 (Avg Bid)
    $55 Ср. ставка
    5 ставки
    Neural network using Verilog Завершено left

    I have a verilog project in which i have to implement neural network to recognize Amazon packages from the given binary matrix image. I already made most of the design code. I am new to verilog and need to finish the project till the final layout.

    $218 (Avg Bid)
    $218 Ср. ставка
    9 ставки
    Building a verilog game Завершено left

    Making a code for snake and ladder in verilog .

    $253 (Avg Bid)
    $253 Ср. ставка
    11 ставки

    Hello, I am looking for FPGA devloper to implement VU33P Bitstream and miner for Grin Cuckatoo algorithm. Bitstream will likely have to be written from scratch but miner can be ported from one of open source GPU miners available. see information bellow on Target FPGA and algorithm. Grin POW Info: [войдите, чтобы посмотреть URL] grin miner - as miner plugin: [войдите, чтобы посмотреть URL] Algo...

    $995 (Avg Bid)
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    13 ставки

    I need a professional engineer to help in writing a technical report with Verilog code

    $207 (Avg Bid)
    $207 Ср. ставка
    11 ставки

    I need professional engineer to help in writing a technical report with Verilog code

    $30 - $250
    $30 - $250
    0 ставки
    Project for Ejiwole O. Завершено left

    hii madam this is sandeep yadav i have 4+ years of experience in fpga designing and embedded systems any small project I will help with less, money

    $19 / hr (Avg Bid)
    $19 / hr Ср. ставка
    1 ставки
    VHDL HAMMING CODE Завершено left

    CREATE A HAMMING ENCODER, DECODER USING VHDL/VEROLOG

    $50 (Avg Bid)
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    18 ставки

    We are an IT consultant company and Online tutoring company One of our client needs assistance in Xilinx Vivado - Verilog Project Please bid if you have expertise in Verilog

    $8 / hr (Avg Bid)
    $8 / hr Ср. ставка
    3 ставки
    Xilinx Vivado - Verilog Project Завершено left

    We are an IT consultant company and Online tutoring company One of our client needs assistance in Xilinx Vivado - Verilog Project Please bid if you have expertise in Verilog

    $3 / hr (Avg Bid)
    $3 / hr Ср. ставка
    1 ставки
    mechatronics Завершено left

    Update and maintain printer control software written in C++ and FPGA code. If you do not have specific skills in mechatronics - e.g. controlling motors, lamps, pumps or other physical items - please do not apply! Specific skills in CNC controllers, piezo electronics, linear encoders, etc will be helpful in this project. The first phase of this project is to take the existing code base - do a code ...

    $30 / hr (Avg Bid)
    Соглашение о неразглашении
    $30 / hr Ср. ставка
    36 ставки
    $40 Ср. ставка
    1 ставки
    FPGA and UNO related Завершено left

    Modify the previous assignment so that, when notified by the microprocessor, a bit string of 32 bits is sent from the FPGA to the UNO using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). A push-button on the FPGA board allows the reset of the FPGA design while another push-button on the FPGA board supports two bit string opti...

    $97 (Avg Bid)
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    5 ставки
    VHDL project Завершено left

    Hi, I currently want to make a music visualizer to be displayed on a monitor using VHDL. The software is Xilinx Vivado. Please send me a message if you would like to further discuss this.

    $447 (Avg Bid)
    $447 Ср. ставка
    11 ставки
    Verilog Netlist Enhancer Завершено left

    A utility that calculates the delay of a path taking into consideration the interconnect effects. The utility accepts a routed DEF file, the technology LEF and the library liberty file. The user has to specify the path cells in a file. A possible format for that file is: INPORT/x AND2_X1/a . . DFF_X2/D Instead of providing the path cells, provide the path starting and ending points. Some resourc...

    $10 - $30
    $10 - $30
    0 ставки
    $56 Ср. ставка
    12 ставки
    Verilog experts needed Завершено left

    I need to create a snake game for my project using verilog on my basys 3 board. I have the codes for it but however the codes that I have is for a 12bits RGB VGA 640 x 480 display. I am using a 16bits RGB OLed 96 x 64 display. I'm having trouble to convert it over can you please help me with it? Or u can just write a completely new program for me too. Attached is the board and the Led is at t...

    $7 - $21
    $7 - $21
    0 ставки
    Verilog expert needed -- 2 Завершено left

    I need to create a snake game for my project using verilog on my basys 3 board. I have the codes for it but however the codes that I have is for a 12bits RGB VGA 640 x 480 display. I am using a 16bits RGB OLed 96 x 64 display. I'm having trouble to convert it over can you please help me with it? Or u can just write a completely new program for me too. Attached is the board and the Led is at t...

    $202 (Avg Bid)
    $202 Ср. ставка
    2 ставки
    VGA CONTROLLER in VERILOG Завершено left

    I need a VGA Controller in verilog. Resolution 160 X 120. VGA controller needs to have its own memory. When the game is started the maze glyph will be loaded into the memory (will only have about 10 glyphs). The controller will need to loop through the shared memory with the 19,200 locations that will tell it the glyph locations and when the character sprite moves.

    $505 (Avg Bid)
    $505 Ср. ставка
    9 ставки
    Verilog expert needed Завершено left

    I need to create a snake game for my project using verilog on my basys 3 board. I have the codes for it but however the codes that I have is for a 12bits RGB VGA 640 x 480 display. I am using a 16bits RGB OLed 96 x 64 display. I'm having trouble to convert it over can you please help me with it? Or u can just write a completely new program for me too. Attached is the board and the Led is at t...

    $44 (Avg Bid)
    $44 Ср. ставка
    1 ставки
    Project for Aamir Sohail N. Завершено left

    Hi Aamir Sohail N., As we discussed, You may continue working on VHDL project I am offeriuing work at INR160/hr with 20 hours for working, so thta You get INR 3200/- as agreed.

    $2 / hr (Avg Bid)
    $2 / hr Ср. ставка
    1 ставки
    Project for Ivan P. Завершено left

    Hi Ivan P., I noticed your profile and would like to offer you my project. We can discuss any details over chat. Hi lvan .how are u pls do u know about the fpga project

    $50 / hr (Avg Bid)
    $50 / hr Ср. ставка
    1 ставки
    Parking Meter Design in VHDL Завершено left

    1.A VHDL model for your Data Path consisting of the following sub-models as also presented and discussed in-class: [войдите, чтобы посмотреть URL] four digit BCD adder that adds to the count of seconds left in the accumulator the additional minutes(in seconds) being purchased by the 5/10/25 cents coins for 300/600/1500secs respectively This four digit adder should also be used to subtract 1 secon...

    $80 (Avg Bid)
    $80 Ср. ставка
    8 ставки

    Basic VHDL coding needed for a project, described below

    $151 (Avg Bid)
    $151 Ср. ставка
    5 ставки