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    1,460 free verilog projects работ(-а,-ы) найдено, цены указаны в USD
    FPGA testbench in Verilog for SDRAM controller using SDRAM model 5 дней(-я) left
    ПОДТВЕРЖДЕН

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    $104 (Avg Bid)
    $104 Ср. ставка
    4 ставки
    Single Core and Five Stage Pipelined MIPS using Verilog 4 дней(-я) left
    ПОДТВЕРЖДЕН

    ...-Programming Language : Verilog HDL. -This project is divided to two parts:- Part 1. Design and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x

    $123 (Avg Bid)
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    10 ставки
    verilog counter 3 дней(-я) left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

    $62 (Avg Bid)
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    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [войдите, чтобы посмотреть URL] file.

    $28 (Avg Bid)
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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $753 (Avg Bid)
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    1 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $189 - $567
    $189 - $567
    0 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $565 (Avg Bid)
    $565 Ср. ставка
    1 ставки

    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

    $296 (Avg Bid)
    $296 Ср. ставка
    11 ставки

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    $628 (Avg Bid)
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    23 ставки
    Vivado Expert Завершено left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

    $27 / hr (Avg Bid)
    $27 / hr Ср. ставка
    9 ставки

    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

    $115 (Avg Bid)
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    3 ставки

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $1689 (Avg Bid)
    $1689 Ср. ставка
    8 ставки
    RISC-V and processors designing Завершено left

    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

    $1282 (Avg Bid)
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    Processor design using Verilog Завершено left

    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

    $108 (Avg Bid)
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    6 ставки

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $750 (Avg Bid)
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    ...Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further requirements (some

    $776 (Avg Bid)
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    - Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements

    $16 / hr (Avg Bid)
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    VHDL or Verilog program Завершено left

    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

    $18 (Avg Bid)
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    1 ставки

    I need to convert a python code to vhdl code using myhdl.i will attach the python code.

    $23 (Avg Bid)
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    2 ставки

    ...Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

    $169 (Avg Bid)
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    3 ставки
    verilog / VHDL or FPGA expert only Завершено left

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    $56 (Avg Bid)
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    24 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1031 (Avg Bid)
    $1031 Ср. ставка
    4 ставки

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [войдите, чтобы посмотреть URL]; a. The source can

    $625 (Avg Bid)
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    find fpga projects Завершено left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    $462 (Avg Bid)
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    Matlab Codnig Завершено left

    I need the matlab developer and verilog developer

    $623 (Avg Bid)
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    17 ставки
    16-point FFT Завершено left

    verilog code for radix-4 16 point fft

    $15 (Avg Bid)
    $15 Ср. ставка
    8 ставки

    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    $16 (Avg Bid)
    $16 Ср. ставка
    4 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $11834 (Avg Bid)
    $11834 Ср. ставка
    2 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $10690 (Avg Bid)
    $10690 Ср. ставка
    1 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $894 - $901
    $894 - $901
    0 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $882 - $882
    $882 - $882
    0 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $884 - $884
    $884 - $884
    0 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $933 (Avg Bid)
    $933 Ср. ставка
    3 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $736 - $883
    $736 - $883
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    reviewing a code Завершено left

    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

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    CS 223 Digital Design: Smart Evacuation Elevator (System Verilog) Ödevin 21 Aralık 2018'e yetişmesi gerekiyor. Ödev hakkında bilgi için lütfen iletişime geçiniz.

    $150 (Avg Bid)
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    LUT optimization of FFT Завершено left

    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

    $154 (Avg Bid)
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    6 ставки
    Verilog Expert Завершено left

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

    $61 (Avg Bid)
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    20 ставки
    Design 4 bit Adder in Verilog Завершено left

    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

    $35 (Avg Bid)
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    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    $140 (Avg Bid)
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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    $179 (Avg Bid)
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    7 ставки
    FPGA Verilog Programming Завершено left

    Need help program FPGA with Artix-7 using Verliog.

    $125 (Avg Bid)
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    5 ставки
    Urgent FPGA Verilog Project Help Завершено left

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    $175 (Avg Bid)
    $175 Ср. ставка
    1 ставки
    Zen Protocol Miner in Verilog/VHDL Завершено left

    Implement the Zen Protocol in the FPGA and update the Mining App

    $1220 (Avg Bid)
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    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions

    $25 (Avg Bid)
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    Make a serial interface system using Verilog

    $48 (Avg Bid)
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    4 ставки