Freelance asic verilog fpga synthesisработы

Фильтр

Мои последние поисковые запросы
Фильтровать по:
Бюджет
по
по
по
Тип
Навыки
Языки
    Статус работы
    4,275 freelance asic verilog fpga synthesis работ(-а,-ы) найдено, цены указаны в USD

    Linux Другое или затрудняюсь ответить Конфигурация прошивки на asic Майнер s9. Перезборка ядра, отключение ограничения на скорость вращения вентиляторов, полное их отключение. Создание прошивки для первичного запуска.

    $155 (Avg Bid)
    $155 Ср. ставка
    1 ставки
    Verilog/Vivado FPGA Help 6 дней(-я) left

    Hey, I have a project that needs to be done in Verilog and Vivado and I'll share details to anyone interested.

    $25 (Avg Bid)
    $25 Ср. ставка
    8 ставки
    Verilog Task on Nexys 4 board 5 дней(-я) left
    ПОДТВЕРЖДЕН

    Just need to design the Snake Gane as per my specifications. I am using Nexys 4 development board.

    $52 (Avg Bid)
    $52 Ср. ставка
    5 ставки
    SERDES RTL DESIGN 5 дней(-я) left

    I'm looking for an experienced SERDES engineer to design a SERDES PCS on ASIC. This PCS will be connected to a PHY(PMA) IP, encoding the data with 8b10 protocol and then transmitting (no receiving) the data out through the PMA, 5Gbps. The data will be received by a Xilinx FPGA GTH Transceiver and then decoded. Therefore the PCS logics shall be compatible

    $57 / hr (Avg Bid)
    $57 / hr Ср. ставка
    9 ставки

    Design and development of non-invasive medical electronics devices that support and ...electronics devices that support and aid medical professionals in data acquisition and communication with expertise on processor/operating system/testing/system validation, FPGA design, integration of medical sensors, porting, middleware and application development.

    $747 (Avg Bid)
    $747 Ср. ставка
    4 ставки
    Project for Loi L. 5 дней(-я) left

    Hi Loi L., I noticed your profile and would like to offer you my project. =================== The details : - my profile : fpga hobbyist newbie / singapore / currently working in a non-technology industry - hardware : - board : DE10-Lite MAX10 10M50DAF484C7G - monitor : HP Compaq LA2205wg, VGA mode 1680x1050-60Hz - OS : Linux distro (Linux

    $50 / hr (Avg Bid)
    $50 / hr Ср. ставка
    1 ставки

    i have attached the document below. And i need this on 21st of october.

    $120 (Avg Bid)
    $120 Ср. ставка
    7 ставки
    Integrate and Program an RF Transmitter 1 день left
    ПОДТВЕРЖДЕН

    ...developing a transmitter with digital modulation schemes with shorter delivery time. We developed all the algorithms required in LabVIEW FPGA. The same have to be ported to VHDL and be integrated before programming the Xilinx V6 FPGA on the transmitter. Complete hardware and many of the software blocks in VHDL are already built by our team. The requirement is

    $861 (Avg Bid)
    Местный
    $861 Ср. ставка
    11 ставки

    Need an expert in xilinx vivado Projects are based on digital systems on topics such as Multiplexers Flip flops registers Counters Clock dividers Please contact for project instructions and further details

    $134 (Avg Bid)
    $134 Ср. ставка
    9 ставки
    Machine learning on FPGA board 6 часов(-а) left

    I have my working model of neural network. I want to develop an accelerator on FPGA and show improvement in power.

    $526 (Avg Bid)
    $526 Ср. ставка
    28 ставки

    ...Video Production Landscape Design Online Writing Financial Analysis Drafting Package Design User Experience Design Moving Swift Autodesk Inventor Tattoo Design Call Center FPGA Handyman Microsoft SQL Server Digital Marketing Wikipedia Zbrush Carpentry Book Artist Procurement Database Development Raspberry Pi Wix VB.NET Sketching Email Developer Network

    $96 (Avg Bid)
    Избранный
    $96 Ср. ставка
    15 ставки

    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

    $78 (Avg Bid)
    $78 Ср. ставка
    5 ставки
    illustration of chemical synthesis Завершено left

    I need to check procedure and I need step by steps drawings of the chemicals reactions.

    $112 (Avg Bid)
    $112 Ср. ставка
    21 ставки
    Task on verilog 3 bit ALU Завершено left

    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

    $63 (Avg Bid)
    $63 Ср. ставка
    22 ставки
    Small task 3 bit ALU using Verilog Завершено left

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

    $28 (Avg Bid)
    $28 Ср. ставка
    3 ставки
    Audio over IP motherboard PCB Завершено left

    We are looking for someone who is very good with high speed digital layouts. The application is an Ethernet to digital audio motherboard. A daughter card with an Zynq FPGA/processor will install on this motherboard, and the motherboard will install onto a DAC board. There is a development board for this daughter card already. So this motherboard will

    $1800 (Avg Bid)
    $1800 Ср. ставка
    18 ставки

    ...Project Framework. Must have good hands-on experience in jQuery Drag-And-Drop UI development and javascript. Should be preferred if someone has worked on Google Speech Synthesis. Must have good expertise in playing around with various JSON functions/objects. REST APIs to be written in Node and Database of the system could be MongoDB or mySQL. (We

    $4071 (Avg Bid)
    $4071 Ср. ставка
    14 ставки
    Labview MyRIO2 Завершено left

    ...in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes that must be run by MyRIO FPGA to analyse the captured

    $144 (Avg Bid)
    $144 Ср. ставка
    3 ставки
    Distance using FPGA Завершено left

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    $117 (Avg Bid)
    $117 Ср. ставка
    21 ставки

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    $16 / hr (Avg Bid)
    $16 / hr Ср. ставка
    30 ставки

    Hello Freelancers! I have this project for aprox $40AUD and due to end of October. We want an application in java with APIs integration, the description states all information on project. I am interested for a freelancer to do the tech part & documentation (that is chapters 4 and 5 of the ATTACHED descritpion) according to the details given in the Objective and Purpose of the description. K...

    $28 (Avg Bid)
    $28 Ср. ставка
    2 ставки
    modify ccminer to work with fpga Завершено left

    I need someone to modify the ccminer software. So it can communicate with FPGAs instead GPUs. It needs to work with both usb and pcie. I'm not asking for algorithm programming, I'm not asking for bitstreams. Just modifying the mining app ccminer so it works with FPGAs.

    $657 (Avg Bid)
    $657 Ср. ставка
    12 ставки
    SRAM FPGA controller in Verilog Завершено left

    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix

    $19 (Avg Bid)
    $19 Ср. ставка
    6 ставки
    Hire a Lead Generator (Oct 2018) Завершено left

    ...property developers, shopping centres, existing businesses sharing a similar name, etc). Suitable targets can be sourced from [войдите, чтобы посмотреть URL], [войдите, чтобы посмотреть URL], Google Search, ASIC, WhoIs, etc b) The Freelancer is to provide to me a spreadsheet with the basic contact details for each target identified above so that contact can be made via email and/or

    $5 / hr (Avg Bid)
    $5 / hr Ср. ставка
    25 ставки
    need freelancer in deepfake Завершено left

    hello we build system in deepfake skiils in "deep learning" artificial intelligence-based human image synthesis technique work with us in same system as freelancer

    $26 (Avg Bid)
    $26 Ср. ставка
    3 ставки
    need freelancer in deepfake Завершено left

    hello we build system in deepfake skiils in "deep learning" artificial intelligence-based human image synthesis technique work with us in same system as freelancer

    $21 / hr (Avg Bid)
    $21 / hr Ср. ставка
    8 ставки
    FPGA craze Завершено left

    coding of bitstreams, software licensing, imbedded commission

    $2372 (Avg Bid)
    $2372 Ср. ставка
    18 ставки
    LabVIEW MyRIO Project -- 2 Завершено left

    ...in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes that must be run by MyRIO FPGA to analyse the captured

    $142 (Avg Bid)
    $142 Ср. ставка
    8 ставки

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    $33 (Avg Bid)
    $33 Ср. ставка
    3 ставки
    FPGA Project I2S to SPI Завершено left

    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

    $211 (Avg Bid)
    $211 Ср. ставка
    3 ставки
    LabVIEW MyRIO Project Завершено left

    ...in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes that must be run by MyRIO FPGA to analyse the captured

    $152 (Avg Bid)
    $152 Ср. ставка
    4 ставки

    An experienced freelancer with rich knowledge in synthesis, argument building and intensive research is need to put together emerging trends in self concept and luxury consumption. A very research article is needed here and speakers of English as first language are preferred.

    $22 / hr (Avg Bid)
    Избранный
    $22 / hr Ср. ставка
    29 ставки
    $140 Ср. ставка
    7 ставки

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    $121 (Avg Bid)
    $121 Ср. ставка
    17 ставки

    ...complete this project. They both have sample projects for HDMI in and HDMI out. What I'm trying to accomplish is have: 1) PC->HDMI->FPGA->HDMI->Monitor 2) PC->USB-> FPGA 3) The PC will send information to the FPGA and create an overlay on the monitor. This software on the PC could be coded in C++ or C. Example, DrawText(x, y, "Truck #19 ready f...

    $361 (Avg Bid)
    $361 Ср. ставка
    7 ставки

    ...Cryptocurrency Algorithms,Cryptocurrency Mining Algorithms,Mined Cryptocurrency,CPU Mining,ASIC-resistant 1. Custom Cryptocurrency Mining Algorithms Development 2. Topic related, you can create a report topic: XXXXXX Algorithm CPU-friendly,GPU-resistant and ASIC-resistant by Design 3. In addition to the text, it is best to have drawings or forms in the

    $525 (Avg Bid)
    $525 Ср. ставка
    4 ставки

    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

    $500 (Avg Bid)
    $500 Ср. ставка
    15 ставки
    DSP Firmware Engineer Завершено left

    We are looking for DSP Firmware Engineer who has specialized in algorithms' performance optimization for DSP/FPGA based on VLIW architecture.

    $10 / hr (Avg Bid)
    $10 / hr Ср. ставка
    2 ставки
    coding in Verilog using Xilinx Завершено left

    Please refer the att...the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

    $43 (Avg Bid)
    $43 Ср. ставка
    13 ставки
    Video converter Завершено left

    I am looking to create hardware that will convert HDMI to NDI (Network Device Interface) I need both hardware and [войдите, чтобы посмотреть URL] is no set date when I need this by but w...HDMI to NDI (Network Device Interface) I need both hardware and [войдите, чтобы посмотреть URL] is no set date when I need this by but would like it soon. There is an sdk for the conversion by fpga.

    $1361 (Avg Bid)
    $1361 Ср. ставка
    4 ставки
    SERDES design on FPGA Завершено left

    ...sent out of the FPGA chip through a single pin... Part 2 ...The serial transmission from part 1 is captured and converted to parallel data before being stored in another memory location( as 16 locations of 8-bits). The data in this memory should match with the data in memory in Part 1. Both parts are to be implemented in the same FPGA ....The serial

    $151 (Avg Bid)
    $151 Ср. ставка
    22 ставки

    I am building a tech blog about FPGA crypto mining. I need someone able to write tech articles, based on my request, about FPGA crypto mining. This is NOT something you can search on google and learn and write. Requirements: 1) You MUST have VERY GOOD knowledge about FPGAs 2) You MUST have VERY GOOD knowledge about crypto mining 3) You MUST be english/american

    $86 (Avg Bid)
    $86 Ср. ставка
    17 ставки
    FPGA/HPS Linux SD Card Image Завершено left

    I have a DE1-SoC FPGA board. I need an image build with a Linux installation (doesn't really matter) and the linux-socfpga kernel; however, the device tree blob on the installation must recognize the onboard FPGA peripherals, especially the onboard ADC. The goal is to have a working Linux image file, which when burned to an SD card would load Linux

    $149 (Avg Bid)
    $149 Ср. ставка
    6 ставки
    Read data sensor Завершено left

    Read data of sensor on FPGA Xillinx. More details via messenger Freelancer.com with full requirements.

    $138 (Avg Bid)
    $138 Ср. ставка
    16 ставки

    ...js framework setup. Must have good hands-on experience in jQuery Drag-And-Drop UI development and javascript. Should be preferred if someone has worked on Google Speech Synthesis. Must have good expertise in playing around with various JSON functions/objects. Backend of the system could be MongoDB or mySql. AGENCIES STRICTLY EXCUSE. Freelancer has

    $2125 (Avg Bid)
    $2125 Ср. ставка
    12 ставки

    1. Identify the background to the case Tengri [войдите, чтобы посмотреть URL] and it’s marketing mix 2. Explain the case and synthesis with theory, consider its product, promotion, place and pricing strategy of Tengri 3. Analyse the situation, provide a positioning analysis of Tengri against its competitors 4. Identify with 20 academic journal references

    $88 (Avg Bid)
    $88 Ср. ставка
    14 ставки
    VLSI Design Engineer - Part Time Завершено left

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $176 (Avg Bid)
    $176 Ср. ставка
    12 ставки

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $149 (Avg Bid)
    $149 Ср. ставка
    4 ставки