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    4,435 freelance asic verilog fpga synthesis работ(-а,-ы) найдено, цены указаны в USD

    ...[войдите, чтобы посмотреть URL] Сайт создан на конструкторе satu.kz. Title Asic Mining в Казахстане – Купить asic для майнинга. Keywords asic, asic miner, купить асик, купить асик в казахстане, asic цена, asic miner купить, купить асик в астане, асик, майнинг, miner, mining, asic майнинг купить, asic майнинг купить, астана май...

    $87 (Avg Bid)
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    Linux Другое или затрудняюсь ответить Конфигурация прошивки на asic Майнер s9. Перезборка ядра, отключение ограничения на скорость вращения вентиляторов, полное их отключение. Создание прошивки для первичного запуска.

    $155 (Avg Bid)
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    Altera FPGA Board Evaluation 6 дней(-я) left

    Hi Freelancers, I have a project I've been working on for the past 2 months- an Altera FPGA control system for a specific application. Although I have knowledge in electrical engineering, I have no qualifications in the field, and thus I’d like a qualified individual to confirm my design, correct any mistakes I may have made, and possibly make the product

    $178 (Avg Bid)
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    Hello I'm looking for a talented FPGA developer who have rich knowledge of mining with several kinds of algorithms and also have experience with it. Looking forward honest developers. Thanks

    $21 / hr (Avg Bid)
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    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with reasonable

    $4310 (Avg Bid)
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    Design several lowpass and high pass filter prototypes using FIR and IIR filters. Design and model the 2-channel analysis and synthesis filter bank using Matlab/Simulink.

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    VHDL/Verilog expert with Virtex-5 board needed 5 дней(-я) left
    ПОДТВЕРЖДЕН

    ...include: • Investigating hardware optimization techniques targeting Xilinx FPGA Devices • Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx

    $197 (Avg Bid)
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    Bug-fix/Update FPGA Miner 4 дней(-я) left

    Bug-fix Mining App and FPGA-VHDL Project. You have to fix the mining App what is written in C and running on a Linux server. And fix on the FPGA side the PLL and add multicores.

    $555 (Avg Bid)
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    Project for Krishna G. 6 дней(-я) left

    ...required knowledge would have to be 1) FPGA bitstreams development 2) Crypto mining software. 3) You MUST have at least one VCU1525 (VU9P Xilinx board) AVAILABLE to be able to develop the bitstream. You will have to use an exhisting open source crypto minign software, developed for GPUs and CPUs, and port it to the FPGA in a VERY EFFICIENT way Very efficient

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    Project for Feifei S. 6 дней(-я) left

    ...required knowledge would have to be 1) FPGA bitstreams development 2) Crypto mining software. 3) You MUST have at least one VCU1525 (VU9P Xilinx board) AVAILABLE to be able to develop the bitstream. You will have to use an exhisting open source crypto minign software, developed for GPUs and CPUs, and port it to the FPGA in a VERY EFFICIENT way Very efficient

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    Project for Iqra Software .. 6 дней(-я) left

    ...have to be 1) FPGA bitstreams development 2) Crypto mining software. 3) You MUST have at least one VCU1525 (VU9P Xilinx board) AVAILABLE to be able to develop the bitstream. The crypto mining software, already exhisting, should be ported to the FPGA in a VERY efficient way. Very efficient means that the hashrate output of the FPGA, once developed

    $1 / hr (Avg Bid)
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    Project for Volvox E. 5 дней(-я) left

    Merhaba, bizim bir projede FPGA mühendisine ihtiyacimiz var ve sizinle bu konuda görüsmek istiyorum.

    $10 (Avg Bid)
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    ASIC FPGA Firmware development 23 часов(-а) left

    We are looking for developers/coders specialized in cryptos and blockchain for a project of firmware development. We would like to get a firmware to overclock this mining hardware i.e. graphic cards (GPU) RX580 8Go. Which are the maximum hashrates performances you can get?

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    Project for Eric D. 3 дней(-я) left

    ...and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing

    $1 / hr (Avg Bid)
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    Project for Feifei S. 3 дней(-я) left

    ...and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing

    $1 / hr (Avg Bid)
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    Project for Amir Y. 3 дней(-я) left

    ...and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing

    $1 / hr (Avg Bid)
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    Project for Muhammad T. 3 дней(-я) left

    Dear Muhammad, I am looking for an Hardware Engineer having experience with FPGA/ASIC in the Ethernet area. We want to build and develop a product and it looks that you would be able to do that. More details about the project I would share in the chat.

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    Project for Ahmed M. 1 день left

    ..."MagicNumber(2 bytes), Length(2 bytes), Payload(252 bytes)" 0xAA 0x55 , 0x00 0xFC , rest 252 bytes data 3. Main clock for FPGA is 50MHz. 4. Data read from FIFO is at main clock (50MHz). 5. Clock cross over should be handled without any data lose. 6. Timing contraints should be properly mentioned

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    verilog / VHDL or FPGA expert only Завершено left

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

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    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

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    PCIE FPGA PCB Design Revision Завершено left

    We require a PCB designer familiar with gerber files and PCI Express FPGA designs. We have a reference design and we require the design simplifying so the board only provides the functions required to run our software as effective as possible.

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    Essay Writing Завершено left

    Hardw...artificial neural networks, machine vision and other machine learning algorithms for robotics, internet of things and other data-intensive or sensor-driven tasks. • SW, GPU, FPGA, ASICs, Heterogeneous computing • Examples: • Virtual machines and environments for NN acceleration • Nvidia Volta/Tesla application for NN acceleration Es

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    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [войдите, чтобы посмотреть URL]; a. The source can

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    ...for someone who can design a FPGA based x16r miner to mine Cuckoo Cycle based coins like rvn. The design should be adaptable for possible changes in the x16r algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with

    $5731 (Avg Bid)
    Соглашение о неразглашении
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    find fpga projects Завершено left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

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    Matlab Codnig Завершено left

    I need the matlab developer and verilog developer

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    Hi, I need a quick prototype for an Artix-7 based fpga that makes a pcie to sd card controller (SD host controller/SD bus). Objective is to have a fpga card (working on pcie screamer) recognized as a SD/MMC card reader under windows, I need Windows to recognize/be able to install the windows built-in sd card drivers for the card. I don’t need it

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    Arduino that can record signal data and playback the data. it will be inline. I have a FPGA and an LCD. I need to record the signals coming from the FPGA to the LCD and recreate the signal to display on the LCD

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    I would like a board designed in Altium Designer, KiCAD or Eagle that is PIN compatible with the ZYBO Z7-20 board from diligent, but has only the essential circuitry required for RAM, Power, Jtag, and the CSI camera. Please and thank you.

    $15 - $25 / hr
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    I would like a board designed in Altium Designer, KiCAD or Eagle that is PIN compatible with the ZYBO Z7-20 board from diligent, but has only the essential circuitry required for RAM, Power, Jtag, and the CSI camera. Please and thank you.

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    GIVE ME SOME IDEAS ABOUT PROJECTS USING FPGA BOARD I need some ideas(NEARLY 10) for my projects by using [войдите, чтобы посмотреть URL] is an electronics and communication engineering project.I need some new ideas. Give me an example idea for accepting the [войдите, чтобы посмотреть URL] should use only fpga and some sensors only.

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    Trophy icon Webpage Photoshop Design for Synergy Corporate 8 дней(-я) left

    ...requirement are similar to Accounting website My Cash Online My cash online is an online money lender who is Regulated by responsible lending of the Australian Government Body ASIC. • An MyCashOnline logo. • A menu bar. • A loan calculator. Allows to choose loan amount and loan period and then calculate the weekly repayment and display the value. In

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    Looking for FPGA developer Завершено left

    Hello I'm looking for a talented FPGA developer who have rich knowledge of C/C++, Python I have a machine using Huawei's FPGA used vu9p core and I am going to port x13bcd hash algorithm to this machine And I want at least 300mh/s with x13bcd but will increase double using x16R I am using Ubuntu and you can check your project via remote Other details

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    fpga image fusion Завершено left

    i want you to do project for medical image fusion of CT scan and MRI using xilinix fpga

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    Animated video Завершено left

    Compare renewable energy sources: a.) Solar b.) Wind c.) Hydro d.) Geothermal Show the cost of producing electr...same as the previous diagram The point we are trying to make here is that geo is perfect for mining because the energy is available all the time. PS: It's a good idea to show ASIC miners or mining rig while showing the mining operation.

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    16-point FFT Завершено left

    verilog code for radix-4 16 point fft

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    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

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    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $11854 (Avg Bid)
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    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $10386 (Avg Bid)
    $10386 Ср. ставка
    1 ставки

    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $894 - $901
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    0 ставки

    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $882 - $882
    $882 - $882
    0 ставки

    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $884 - $884
    $884 - $884
    0 ставки

    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $896 (Avg Bid)
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    3 ставки

    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $736 - $883
    $736 - $883
    0 ставки
    Add a connector into PCB layout Завершено left

    I have a 4 layers PCB fully done in Alti...to connect a new EXP main connector to the FPGA. Some nets may be missing in schematics, you should manually add the net names to the schematics. Although the schematic need slight fix, the PCB's DRC is ok, no errror. The EXP connector is DIL 2x12 2.54mm pitch, where signals have to be connected to the FPGA..

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    Hello, I have a set of ECG signal values in numeric form, I want to display them throu...want to display them through Xlinx code and send the same signal to network device through wifi. Please let me know if you can do it in 2 days. The code will not run on actual FPGA board, its just a simulation project. The code should run on xilinx ise software.

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    FPGA XC6SLX25, Power source 12v. Connect PROM(at least 2 megabyte) and RAM(at least 100kilobyte) to FPGA and power

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    FPGA project Завершено left

    i need someone to take a FPGA and make it compatible with a MIPI LCD.

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