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    1,481 freelance projects usa verilog работ(-а,-ы) найдено, цены указаны в USD

    I want to do image processing for some of my images its basically a red color segmentation from the image and detect the patterns using verilog..... the image size is 240x240

    $279 (Avg Bid)
    $279 Ср. ставка
    7 ставки

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    $200 (Avg Bid)
    $200 Ср. ставка
    1 ставки

    This project need to implement the several LVDS interf...after simulating transfer (Buffer content ==> FPGA RAM content) This is the testing project, so that, you can get more projects after completing this. If you have experiences, you can complete within a few days. Deliverables: Verilog & buffer frame communication simulation in Xilinx Vivado

    $377 (Avg Bid)
    $377 Ср. ставка
    5 ставки

    The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC. As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.

    $1308 (Avg Bid)
    $1308 Ср. ставка
    15 ставки
    Project for olegkaravaev84 4 дней(-я) left

    Hi olegkaravaev84, I noticed your profile and would like to offer you my SystemVerilog/Verilog FP{GA project. We can discuss any details over chat.

    $450 / hr (Avg Bid)
    $450 / hr Ср. ставка
    1 ставки

    an expert on FPGA and Verilog should bid only...

    $155 (Avg Bid)
    $155 Ср. ставка
    13 ставки
    Verilog Design 18 часов(-а) left

    I have one architecture, needs the RTL verilog code for the design to be made and followed by placement and routing to derive the power.

    $138 (Avg Bid)
    $138 Ср. ставка
    10 ставки
    Vivado HLS fixed point code optimization 14 часов(-а) left
    ПОДТВЕРЖДЕН

    1. Vivado HLS fixed code optimization 2. Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HL... Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HLS 5. Intergration of IP generated in HLS in Verilog code

    $181 (Avg Bid)
    $181 Ср. ставка
    1 ставки
    build mac unit Завершено left

    build mac unit using verilog language. I have already done the multypler part and I need help to build the rest

    $38 (Avg Bid)
    $38 Ср. ставка
    9 ставки
    verilog skills required Завершено left

    Basically I would like to have the verilog coding to build on my basys3 hardware. required to control the LED with left and right pushbutton within a range, to code different frequency for the LED within that range, to code one letter on each 7segment and the speed of the letter being displayed is depend on the frequency coded to the led. to code a

    $26 (Avg Bid)
    $26 Ср. ставка
    4 ставки

    FPGA mining hardware - Xiling FPGA - Nexys Video - Can be leveraged from open source bitcoin miner code. - Based on Verilog. - Provide source code, constraints and full recipe for synthesis, implementation and bitstream generation - Connectivity via JTAG to the host (via USB). May consider UART instead, but as a less desirable solution. Mining software:

    $565 (Avg Bid)
    $565 Ср. ставка
    8 ставки
    FPGA verilog Завершено left

    Using ModelSim or Quartus II for solving some problems i am working on

    $27 (Avg Bid)
    $27 Ср. ставка
    17 ставки

    Code will contain encryption and decryption of elliptic curve cryptography

    $111 (Avg Bid)
    $111 Ср. ставка
    1 ставки

    Hi, we have project for creating simple RISC processor through vhdl/Verilog. If interested will give more information

    $10 / hr (Avg Bid)
    $10 / hr Ср. ставка
    1 ставки

    VHDL/Verilog basic RISC Processor, will give more details if interested

    $7 / hr (Avg Bid)
    $7 / hr Ср. ставка
    1 ставки
    Port c code to Verilog (for FPGA) Завершено left

    This project consists to port some c code (around 50 lines) to Verilog in order to run on a FPGA. Output of the contest Verilog .v source file equivalent of verilog.c testbench .v file equivalent to doSimulation() You can run the C code with "gcc main.c && ./[войдите, чтобы посмотреть URL]" Elements to select the winning bidder: - Partial screenshot of the implem...

    $67 (Avg Bid)
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    8 ставки

    ...with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x 32) 2- ALU 3- Instruction Register 4- Control Unit 5- PC register 6- Shift logic unit 7- Conditional logic unit 8- Three-level Cache for the Data

    $316 (Avg Bid)
    $316 Ср. ставка
    6 ставки

    matrix multiplication using strassenalg and karatsuba alg and carry select adder

    $41 (Avg Bid)
    $41 Ср. ставка
    6 ставки

    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting

    $13 / hr (Avg Bid)
    $13 / hr Ср. ставка
    11 ставки

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    $104 (Avg Bid)
    $104 Ср. ставка
    4 ставки
    verilog counter Завершено left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

    $62 (Avg Bid)
    $62 Ср. ставка
    7 ставки

    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [войдите, чтобы посмотреть URL] file.

    $28 (Avg Bid)
    $28 Ср. ставка
    9 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $759 (Avg Bid)
    $759 Ср. ставка
    1 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $189 - $567
    $189 - $567
    0 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $565 (Avg Bid)
    $565 Ср. ставка
    1 ставки

    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

    $296 (Avg Bid)
    $296 Ср. ставка
    11 ставки

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    $628 (Avg Bid)
    $628 Ср. ставка
    23 ставки
    Vivado Expert Завершено left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

    $27 / hr (Avg Bid)
    $27 / hr Ср. ставка
    9 ставки

    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

    $115 (Avg Bid)
    $115 Ср. ставка
    3 ставки

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $1689 (Avg Bid)
    $1689 Ср. ставка
    8 ставки
    RISC-V and processors designing Завершено left

    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

    $1279 (Avg Bid)
    $1279 Ср. ставка
    13 ставки
    Processor design using Verilog Завершено left

    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

    $108 (Avg Bid)
    $108 Ср. ставка
    6 ставки

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $750 (Avg Bid)
    $750 Ср. ставка
    1 ставки

    ...Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further requirements (some

    $776 (Avg Bid)
    $776 Ср. ставка
    9 ставки

    - Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements

    $16 / hr (Avg Bid)
    $16 / hr Ср. ставка
    11 ставки
    VHDL or Verilog program Завершено left

    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

    $18 (Avg Bid)
    $18 Ср. ставка
    1 ставки

    I need to convert a python code to vhdl code using myhdl.i will attach the python code.

    $23 (Avg Bid)
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    2 ставки

    ...Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

    $168 (Avg Bid)
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    3 ставки
    verilog / VHDL or FPGA expert only Завершено left

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    $56 (Avg Bid)
    $56 Ср. ставка
    24 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1031 (Avg Bid)
    $1031 Ср. ставка
    4 ставки

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [войдите, чтобы посмотреть URL]; a. The source can

    $625 (Avg Bid)
    $625 Ср. ставка
    3 ставки
    find fpga projects Завершено left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    $462 (Avg Bid)
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    10 ставки
    Matlab Codnig Завершено left

    I need the matlab developer and verilog developer

    $623 (Avg Bid)
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    17 ставки
    16-point FFT Завершено left

    verilog code for radix-4 16 point fft

    $15 (Avg Bid)
    $15 Ср. ставка
    8 ставки

    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    $16 (Avg Bid)
    $16 Ср. ставка
    4 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $11834 (Avg Bid)
    $11834 Ср. ставка
    2 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $10690 (Avg Bid)
    $10690 Ср. ставка
    1 ставки