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    114 modelsim работ(-а,-ы) найдено, цены указаны в USD
    Microprocessor using verilog Завершено left

    Microprocessor design project using system verilog in Modelsim and physical validation on Quartus Prime. I have started writing code for some of the blocks. The Register file, ALU and Instruction memory are nearly complete. Assistance needed in writing the remainder of the blocks: the instruction register, the micro controller unit, the W register, the program counter and anything else needed to w...

    $139 (Avg Bid)
    $139 Ср. ставка
    5 ставки

    Using Altera DE1-SoC FPGA board, I want you to write a code which can do FFT of the provided signal using Quartus II and Modelsim.

    $344 (Avg Bid)
    $344 Ср. ставка
    7 ставки

    The distance measurement with help of MB1010 ultrasonic distance sensor ( [войдите, чтобы посмотреть URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core ([войдите, чтобы посмотреть URL]) is to be used, which takes over the control. The result of the distance measurement should be displayed on 7-segment displays. Pressin...

    $265 (Avg Bid)
    $265 Ср. ставка
    2 ставки
    FPGA verilog Завершено left

    Using ModelSim or Quartus II for solving some problems i am working on

    $28 (Avg Bid)
    $28 Ср. ставка
    15 ставки

    In this project, a simple VGA (Video Graphics Array) controller shall be implemented using an FPGA Basys3. The VGA controller should be able to display images with a resolution of 640X480 pixels. Furthermore, it should be possible to select between two different images, depending on the position of switch SW1. Document description of whole design including images explanation of Testbench with...

    $110 (Avg Bid)
    $110 Ср. ставка
    2 ставки

    -Tools:Altera Quartus,Modelsim and FPGA. -This Project is divided to two parts:- [войдите, чтобы посмотреть URL] and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x 32) 2- ALU 3- Instruction ...

    $316 (Avg Bid)
    $316 Ср. ставка
    6 ставки

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    $104 (Avg Bid)
    $104 Ср. ставка
    4 ставки
    Digital Design - VHDL Programm Завершено left

    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit should be initialized with a high-active rese...

    $43 (Avg Bid)
    $43 Ср. ставка
    11 ставки
    VHDL - Programming Digital Design Завершено left

    Digital Circuit will be represented and simulated via ModelSim simulator. Consider the digital circuit represented below. Two eight-bit wide data input ports are added. The result is then used to set one of eight output lines according to predefined thresholds. Code this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the...

    $29 (Avg Bid)
    $29 Ср. ставка
    10 ставки

    Hello freelancers! The goal of this project is to help us investigate hardware-efficient implementation of the Espresso stream cipher and to compare it to Grain-128 and Trivium in terms of area, delay, latency and power energy consumption so we can decide which suits us the best. Your tasks will include: • Investigating hardware optimization techniques targeting Xilinx FPGA Devices ...

    $167 (Avg Bid)
    $167 Ср. ставка
    3 ставки
    Project for Loi L. Завершено left

    Hi Loi L., I noticed your profile and would like to offer you my project. =================== The details : - my profile : fpga hobbyist newbie / singapore / currently working in a non-technology industry - hardware : - board : DE10-Lite MAX10 10M50DAF484C7G - monitor : HP Compaq LA2205wg, VGA mode 1680x1050-60Hz - OS : Linux distro (Linux Mint). - language : VHDL - IDE : Quartus Prim...

    $50 / hr (Avg Bid)
    $50 / hr Ср. ставка
    1 ставки

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    $33 (Avg Bid)
    $33 Ср. ставка
    3 ставки
    VLSI Design Engineer - Part Time Завершено left

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate should be familiar with solving IEEE r...

    $185 (Avg Bid)
    $185 Ср. ставка
    12 ставки

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate should be familiar with solving IEEE r...

    $153 (Avg Bid)
    $153 Ср. ставка
    3 ставки

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    $434 (Avg Bid)
    $434 Ср. ставка
    2 ставки
    Do VHDL project on the ModelSim Завершено left

    I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir...

    $158 (Avg Bid)
    $158 Ср. ставка
    9 ставки

    I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this task by next Sunday, 22nd April before I starte...

    $42 (Avg Bid)
    $42 Ср. ставка
    7 ставки
    projects about MIPS and ModelSim Завершено left

    a very small project but need to know how to use MIPS and Modelsim

    $30 (Avg Bid)
    $30 Ср. ставка
    2 ставки
    Digital Alarm clock "verilog " Завершено left

    I am looking for a freelancer to help me with my project. The skill required is Verilog. Project is to write verilog code for digital alarm clock an will be simulating in Modelsim and will need testbenches as well. message me for more details

    $57 (Avg Bid)
    $57 Ср. ставка
    13 ставки
    Analogue and Digital Electronic 1 Завершено left

    Analogue and digital Electronic which involves calculations, VHDL code using Modelsim software only. Please kindly read the attached file very well and know what it is involved before placing a bid.

    $223 (Avg Bid)
    $223 Ср. ставка
    8 ставки
    Modelsim VHDL -- 2 Завершено left

    I need you to develop some software for me. I would like this software to be developed . Modelsim VHDL

    $82 (Avg Bid)
    $82 Ср. ставка
    6 ставки
    Modelsim VHDL Завершено left

    I need you to develop some software for me. I would like this software to be developed . Modelsim VHDL

    $10 - $30
    $10 - $30
    0 ставки

    Hi, I wanted to implement research work on the AES(Advnaced Encryption Standard) algorithm and differential scan attack on the same to retriever secret key. In addition, the prevention mechanism against such attack has to be developed. Coding and simulation in verilog(Xilinix-ISE/Modelsim) will be fine. Also, requires documents for the implementation (step-by-step procedure), block diagram ...

    $946 (Avg Bid)
    $946 Ср. ставка
    4 ставки

    The conventional (single-match) priority encoder finds only one match, i.e. the highest priority input. An n-bit MPZ unit finds r (1 ≤r≤n) matches in exactly r cycles. Design an 8-bit MPZ using HDL description. You may use ModelSim or Quartus II software. In your implementation, you may have a mix of behavioral and structural descriptions for modules/components. Slight modification...

    $25 (Avg Bid)
    $25 Ср. ставка
    1 ставки

    The conventional (single-match) priority encoder finds only one match, i.e. the highest priority input. An n-bit MPZ unit finds r (1 ≤ r ≤ n) matches in exactly r cycles. Design an 8-bitMPZ using HDL description. You may use ModelSim or Quartus II software. In your implementation, you may have a mix of behavioral and structural descriptions for modules/components. Slight modifications of t...

    $37 (Avg Bid)
    $37 Ср. ставка
    8 ставки
    VHDL assignment help Завершено left

    I have an assignment that my lecturer asked me to do and the deadline is 28/7/2017. I need to show him the simulation that the program is running and may be few basic question. I want someone to do the assignment and show me how I have to show to my teacher that the program is running (simulation). I have attached a file where there is 3 question. But I only need to solve question 2. That is "...

    $29 (Avg Bid)
    $29 Ср. ставка
    2 ставки

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    $69 (Avg Bid)
    $69 Ср. ставка
    20 ставки

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim

    $158 (Avg Bid)
    $158 Ср. ставка
    9 ставки

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim

    $555 (Avg Bid)
    $555 Ср. ставка
    2 ставки
    Asic design - verilog/HDL code Завершено left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    $173 (Avg Bid)
    $173 Ср. ставка
    21 ставки

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    $157 (Avg Bid)
    $157 Ср. ставка
    12 ставки

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    $190 (Avg Bid)
    $190 Ср. ставка
    9 ставки
    Verilog-HDL Code using Modelism -- Завершено left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    $183 (Avg Bid)
    $183 Ср. ставка
    9 ставки
    Verilog-HDL Code using Modelism Завершено left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    $155 (Avg Bid)
    $155 Ср. ставка
    8 ставки

    must know how to code in SystemVerilog Using Quartus, and ModelSIM Setting for Quartus: Family: Arria II GX Device: EP2AGX45DF29I5 I already have started this and need help completing it Check PDF 6 (attached file) for more instructions. It is the project 4. Look through other PDFs to get a clearer idea of what can and cannot be done. use the "hints" provided in pdfs 7,8...

    $46 (Avg Bid)
    $46 Ср. ставка
    3 ставки

    SystemVerilog Using Quartus, and ModelSim Need to design the entire sha1 module (Design the yellow box) [войдите, чтобы посмотреть URL] *There are more files that I will provide

    $250 (Avg Bid)
    $250 Ср. ставка
    1 ставки

    Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfa...

    $19 / hr (Avg Bid)
    $19 / hr Ср. ставка
    9 ставки

    - To design the VHDL based temperature controller that comprises of SPI controller, Data converter, Memory block and Display drivers. - To develop the test bench to test the design for both behavioral and timing model using Modelsim. -Implement the design in FPGA and accomplish the hardware testing.

    $229 (Avg Bid)
    $229 Ср. ставка
    9 ставки

    - To design the VHDL based temperature controller that comprises of SPI controller, Data converter, Memory block and Display drivers. - To develop the test bench to test the design for both behavioral and timing model using Modelsim. - Implement the design in FPGA and accomplish the hardware testing. (optional)

    $10 - $30
    $10 - $30
    0 ставки
    Napisz oprogramowanie Завершено left

    Write testbench for testing digital thermometer DS1624 in VHDL (modelsim), I2C serial communication, and simulation of temperature measurement / extortion file /and read memory.

    $23 (Avg Bid)
    $23 Ср. ставка
    2 ставки
    VHDL - 01/12/2016 13:10 EST Завершено left

    I am an student studying Electrical and Information technology and at present doing a small project in VHDL is which is must as a part of our curriculam for which we are credited. As i am a newbee in VHDL i need a support for completing my project .Although i have managed to do some parts of my project myself , i have less time to complete it on time. Therefore i am looking for a Freelancer who i...

    $299 (Avg Bid)
    $299 Ср. ставка
    9 ставки
    Build an ALU with testbench Завершено left

    Build an ALU with testbench. Compile in Quartus to get size and timing information. Simulate in ModelSim

    $30 (Avg Bid)
    $30 Ср. ставка
    15 ставки
    Matrix Multiplier Project-VHDL Завершено left

    The project must meet certain requirements. Firstly the project (VHDL design and VHDL testbench must be completely free of syntax errors. The VHDL project must synthesise with no problems, such as non-synthesisable code, latch inferred and multi-driver. Must show correct results from behavioural simulation and post-route simulation, in which the post-route delay can be observed. Must have the best...

    $61 (Avg Bid)
    $61 Ср. ставка
    6 ставки

    we are using the proposed techniques to reduce leakage power such as MTCMOS ( Multi threshold CMOS technique), Power Gating, Dual Stack, GALEOR and LECTOR. RCA and CLA circuita designed by using the above mentioned techniques, power dissipation is calculated for each technique and is compared with general CMOS logic of RCA and CLA. Simulation results show the validity of the proposed techniques is...

    $111 (Avg Bid)
    $111 Ср. ставка
    1 ставки

    Project : " Implementation of Left looking LU decomposition Algorithm on FPGA using verilog". I need to do simulation work mainly on "Xilinx or modelsim" software ...I have a working Matlab code for the algorithm . The thing which is to be done is digital suggest a design for this algorithm and then write a verilog code for the same . The simulation have to be done for correc...

    $180 (Avg Bid)
    $180 Ср. ставка
    4 ставки
    Write some Software Завершено left

    Write a complete SYSTEM VERILOG code and TEST BENCH to implement a pipeline processor with 18-bit wide instruction using modelsim student edition software. All modules for the pipeline design are to be written as separate .sv files within a single project file.

    $154 (Avg Bid)
    $154 Ср. ставка
    2 ставки
    16-bit floating point adder Завершено left

    Design a 16-bit floating adder in VHDL. Modelsim for simulation and quartus for synthesis

    $155 (Avg Bid)
    $155 Ср. ставка
    1 ставки

    Hello, we need simple VHDL coding for register/memory and buses for a simple processor. Codding and simulation in modelsim. I will send you documents after bid.

    $154 (Avg Bid)
    $154 Ср. ставка
    7 ставки

    RF signal generator PCB - RF spectrum analyzer PCB. The project require Advanced Design System (ADS) - Agilent / Keysight RF PCB design or equivalent RF simulation. The PCB require specifically RF design skills. More details on PM. C, C++, MATLAB, VHDL, VDSP, ModelSim are a plus.

    $1500 - $3000
    Избранный Скрытый Соглашение о неразглашении
    $1500 - $3000
    11 ставки

    pls check the attachment.. i want this to be done fast

    $22 (Avg Bid)
    $22 Ср. ставка
    4 ставки