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    542 rgmii altera работ(-а,-ы) найдено, цены указаны в USD

    Развести DDR3, топология FlyBy, 2 чипа Altera SoC. 8 слоев (S-P-P-S-S-P-P-S), для разводки DDR доступно 3 (4, 5, 8 слои). Допустимо изменение размещения компонентов, если критично. Правила по выравниванию и классы сигналов заданы. Срок до 28.02. Возможно расширение заказа до полной разводки платы с увеличением стоимости и расширением сроков.

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    Цветомузыка. Адресная светодиодная лента, фильтр по частотам (высокие, средние, низкие), в зависимости от громкости и частоты мигает лента разными цветами

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    Altera De1 SoC FPGA 4 дней(-я) left

    Write a program using QUARTUS ALTERA to work on De1-SoC FPGA BOARD. .................. The LED Brightening Control with an Absolute Encoder The circuit to be designed must provide control of the brightness of a single or multiple LED ‘s using values from an Absolute Contacting Encoder (128 positions). In addition, the circuit must display a decimal value of the LED intensity (0-127) by using three seven-segment displays. The circuit contains four logic blocks and 3 external components (Figure 1). The logic circuits are: • Code Conversion Table • Binary to BCD 3 digits (Decimal Values) • LED Brightening Control (PWM) • Seven Segments Decoder

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    Traffic Control System Завершено left

    Traffic Control System (Two intersection road) using VHDL in Quartus II. Write Code, test bench and simulate in Modelsim Altera. Draw Flow diagram or ASM chart and Mnemonic document state diagram.

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    In this project I want to see how the ADC works in FPGA kit .. with any sensor LED or temp. The board is ALTERA Cyclone IV EP4CE6e22cb

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    aplicativo energia solar Завершено left

    preciso criar um aplicativo para conectar nos aparelhos solar para puxar o consumo do cliente ver detalhes quanto tempo gero energia , gráfico de produção de energia tem que ser dois app um para cliente visualizar quanto esta a produção e outro app para criar o acesso do cliente altera a senha do cliente e visualizar todos o cliente quanto estão consumido

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    ...estão no Woocommerce. Seria mais ou menos uma lista criada por blocos e linha, blocos seria para especificar manualmente uma categoria e na linha o nome do produto colocado manualmente e uma opção para procurar e selecionar o produto que ser vinculado a essa linha, uma vez vinculado vai aparecer na frente o preço e sua variável para ser selecionada caso tenha e uma vez alterado o preço ele também altera e salva no Woocommerce, nessa opção era bom ter um botão para salvar e excluir a linha. Uma vez a linha feita logo abaixo poderia ter o botão de mais para adicionar novas linhas ou blocos. Tudo isso feito é preciso gerar um shortcode ou algo do tipo para gerar um html e ser publicado em uma pagina...

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    Quartus Altera/INTEL Завершено left

    Looking for a tutor on Quartus Altera/Intel MAX10 FPGA device. Knowledge of QSYS, Platform designer, Eclipse, HDL/VHDL. Embedded system control design using FPGA. Closed loop control ADC sampling, PI controller , PWM generation in HDL/VHDL.

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    Looking for website content for Power electronics converter for battery chargers for EV market. Magnetics design , Embedded software FPGA. Altera/Intel VHDL.

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    VHDL SD card implementation Завершено left

    Hello, In my project I need to store data on my FPGA Altera EVMs. The data must be stored on a non-volatile device (power done can occur at all time). To do that, I need to implement an interface to the on board uSD card. Here are some specification: 1. SD Card: Class 10, 2GB. 2. Min write speed: 200Byte every 1ms (effective) ~1.6Mbps. 3. Read speed: 10Mbps (Flash all mode) 4. All VHDL (NiosII- only when guaranteed performance). 5. Full Duplex- Optional. 6. Target: DE10-Nano and DE2-115. 7. Delete all data function: optional. Thanks, Idan

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    Preciso de ajuda para poder trabalhar com meu programa, tenho placa de video geforce940mx configurações compativeis, e o programa trava muito, baixei um programa para fazer checkup dos requisitos e la diz que estou usando uma placa intel e que poderia melhorar usando a nvidea, mas faço a alteração nas definições da nvidia, e faco o checkup novamente mas nao altera.

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    FPGA I2C module Завершено left

    prepare a I2C module for Altera FPGA

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    - A aplicação parou de funcionar devido a alteração de nomes de parâmetros do WhatsApp. - Necessário verificar quais parâmetros pararam de funcionar e altera-los de acordo com os atuais - Criar documentação técnica e funcional da aplicação já desenvolvida para melhorar o suporte. - Funcionalidade da aplicação: A aplicação já desenvolvida apenas exporta os números das conversas do whatsapp que não possuem na agenda (novos números)

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    VHDL , QUARTUS , MODELSIM ALTERA, QUESTASIM, UP DOWN COUNTER , COUNT ZERO COUNTER, CLOCK GENERATOR, RGB CONTROLLER. STATE MACHINE ...

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    The AD 9254 is to be interfaced with TERASIC DE4(Altera startix IV) in DSP builder platform

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    Hi I need an expert in these two software Altera Quartus II Computer Aided Design Software and Modelsim-Altera Simulation Software. inbox me for more details.

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    1. Encode key presses on a standard 16-key 2. give a stable 4-bit binary output 3. Have output to indicate when a key is being pressed.

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    ...them by finding the optimal parameters for all algorithms using a genetic algorithm approach or some other optimisation technique. A developer should know python and the implementation should be done in Google Colab. After that, the best scoring algorithms need to be implemented on FPGA (with a novel approach and MINIMAL hardware resources to avoid inefficient implementation). We strictly use FPGA Altera DE2-115 (VHDL implementation only no Verilog) with and Intel Quartus Prime 18.1 + ModelSim 10.5b edition. After successful implementation and testing in Quartus 18.1, appropriate functional and timing simulation need to be done in Model Sim 10.5b. SECOND PART: It includes the implementation of a successful FPGA prototype on ASIC making an ASIC-based program to test such implemen...

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    DDR3 layout in Altium Завершено left

    Dissolve DDR3, FlyBy topology, 2 Altera SoC chips. 8 layers (S-P-P-S-S-P-P-S), 3 (4, 5, 8 layers) available for DDR wiring. Changing the placement of components is acceptable if critical. Alignment rules and signal classes are defined. Deadline until 28.02. It is possible to expand the order to a complete layout of the board with an increase in cost and extension of terms.

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    Tampermonkey - Script jogo Browser Завершено left

    Preciso traduzir o script é altera algumas ações de acordo com minha necessidade tbm quero mudar sua interface para diminuir a poluição visual! Aceito dicas!! Então preciso das seguintes alterações: Traduzir todo código é nomes para português Mudar a interface "Painel" para diminuir a poluição visual é facilitar o uso! Corrigir algumas funções existente é tira os erros é má funcionamento. Tudo que precisa ser feito esta descrito abaixo: Adicionar as seguintes funções; 1) Compras Joias no leilão quando atingir certa quantidade na mão! 2) Compra merc Leilão quando tiver (X) valor em atributo (X) 3) Ven...

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    Embedded Programming Завершено left

    We are looking for a developer who has experiance in Embedded Application Programming. Typical Operating Systems Embedded Linux Android FreeRTOS μC/OS ARM, MIPS, Motorola, ST, TI, Microchip... Arduino Xilinx MicroBlaze (Softcore Processor) Xilinx and Altera FPGA (see Electronics Overview) Identifying and removing bottlenecks with performance analysis and tracing tools. Using low-level languages such as C or assembler for greater control over resource usage. Developing unit tests to quickly verify software modules on higher performance machines. Tuning code for low memory usage and looking for memory leaks using tools such as Valgrind. Preventing memory leakage by using static allocation if necessary (for example in a safety critical application). can develop user interfaces...

    $250 - $750
    Скрытый Соглашение о неразглашении
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    I need guidance with Altera Quartus and introductory Logic Design/Electrical Engineering work.

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    I need a project made with the software Quartus. My board is using an Altera chip, model: EP4CE6E22C8N. I need a 8 bit calculator, that uses a matrix 4x4 keyboard and display the results in the 7 seegments display that my board has. Board model: RZ-easyfpga a2.2 I attached on the job the pin diagram of my board.

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    ...plasticos transparentes (adjuntos) y tambien en pagina web y redes sociales. Frutalnat produce y comercia frutas y verduras deshidratadas, algunas cosechadas de forma autonoma y otras compradas y deshidratadas de forma natural mediante aire caliente, conservando las carcateristicas organicas , de sabor, textura y color del alimento. Frutalnat NO abandona los productos al sol ya que dicho proceso altera la calidad del deshidratado. Algunos productos deshidratados son: frutillas, damascos (albaricoque), duraznos (melocoton), manzanas verdes, manzanas rojas, acelgas(remolacha de hojas), naranjas, espinaca, tomates, zanahoria, habas Debe apuntar a un publico joven e innovador que valore productos de calidad, saludables conservados de forma natural. Also in english...

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    Altera Schematic Design Завершено left

    Expert using Altera Schematic Design

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    Gateway de pagamento mercadopago - Integrar meu sistema de pagamento com mercadopago Fluxo: 1 - Preciso listar 3 opções de assinatura - Mensal -Semestral -Anual 2 - Usuário clica redirecionado para o mercadopago. 3 - Mercadopago dá o retorno e altera o status numa tabela (Data do pagamento, forma de pagamento, ) Já existe um sistema com essas tabelas... não preciso que faça front para elas: ___________________ Tabela: tbl_pessoa ___________________ -cod_pessoa -ds_nome ___________________ Tabela: Assinatura ___________________ -cod_produto_assinado -ds_produto_assinado -periodicidade -nu_valor ---------------------------------------------------------- Tabela: Pagamentos_de_assinatura ---------------------------------------------...

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    My name is Idan and I'm electronic engineer student. In my application I need to implement a standard VHDL TCP/IP communication. In order to do that we need to interface the Altera Triple Speed Ethernet IP core. The the code, that will interface the Altera TSE IP core, will be commplitly managed by the VHDL side, with fully handshake for max speed. The minimum performent of the system will be throughput of 300Mps @ 1000Mbps linke @ full duplex mode. I've recently bought the DE2-115 EVM and I want to implement the on board Ethernet (with On-Board PHY Chip). The code will be evaluated with Wireshark (Optional: loop back between the two ports. I'm bacically want to have a quick ademenstration on any board that you'll have before adjust it to my project.

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    Cross-compile MT7688 CPU kernel, with enabled and working PCI express, write simple step-by step documentation, MT7688 must detect PCIx card connected, draw simple schematic with all necessary elements.

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    FPGA/Altera Завершено left

    I am looking for an expert in following: Cross-compile MT7688 CPU kernel MT7688 32/128MB CPU Quartus project,

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    1. Cross-compile MT7688 CPU kernel, with enabled and working PCI express, write simple step-by step documentation, MT7688 must detect PCIx card connected, draw simple schematic with all necessary elements. 2. Make sample Quartus project, and write test app : 2.a. Use Hard IP pci x core on Cyclone IV, for example EP4CGX15 or similar 2.b Map PCI device memory space to read/wite access from MT7688 using DMA. Payload can be fixed size >=128 bytes per single R/W transaction. 2.c Write simple C program for OpenWrt to access PCI express device mapped memory read/write data using DMA. Project can be split to 2 parts. 1. and 2. If you can do only one part, contact us.

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    Simulated FPGA trojan Завершено left

    As part of a technology demonstration project, we need a simulated malicious trojan embedded in some open source application (such as PipeCNN) running on an FPGA, preferably on a Terasic DE5-Net Altera Stratix V GX FPGA board. The simulated trojan should, upon trigger, use the PCIe bus to write a random value to some system RAM location (without causing the system to crash in process).

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    My name is Idan and I'm electronic engineer student. In my application I need to implement a standard VHDL Triple Speed Ethernet Altera IP. I've recently bought the DE2-115 EVM and I want to implement the on board Ethernet (with On-Board PHY Chip).

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    Project for Duc D. Завершено left

    Hi Duc D., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $30 / hr (Avg Bid)
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    Project for Khanh L. Завершено left

    Hi Khanh L., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $20 / hr (Avg Bid)
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    Project for Kevin N. Завершено left

    Hi Kevin N., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $19 / hr (Avg Bid)
    $19 / hr Ср. заявка
    1 заявок(-ки)
    Project for Tiep N. Завершено left

    Hi Tiep N., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $20 / hr (Avg Bid)
    $20 / hr Ср. заявка
    1 заявок(-ки)
    Project for Lic T. Завершено left

    Hi Lic T., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    PHP
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    Project for Quang T. Завершено left

    Hi Quang T., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $18 / hr (Avg Bid)
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    Project for Huy L. -- 2 Завершено left

    Huy, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $20 / hr (Avg Bid)
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    1 заявок(-ки)
    Project for Hong L. Завершено left

    Hi Hong L., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $15 / hr (Avg Bid)
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    Project for Van Phu H. Завершено left

    Van Phu, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là mot bay sau khong chin bay nam chin ba bay tam. Locson

    $10 / hr (Avg Bid)
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    1 заявок(-ки)
    Project for Quan D. Завершено left

    Quan, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là mot bay sau khong chin bay nam chin ba bay tam. Locson

    $10 / hr (Avg Bid)
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    1 заявок(-ки)
    Project for hoangvsm Завершено left

    Long, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $5 / hr (Avg Bid)
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    1 заявок(-ки)
    Project for Long D. Завершено left

    Long, ti6i cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $5 / hr (Avg Bid)
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    Hello, I need to implement a TCP/IP protocol between a PC and Altera FPGA for one of my project. Please bid if you're an expert and already you have the proven results with you.

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    FPGA based task Завершено left

    FPGA based task on ALtera board

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    System Verilog Task Завершено left

    System Verilog Task for ALtera FPGA board

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    system verilog code for FPGA Завершено left

    system verilog code for ALtera FPGA Board

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    Need a Verilog expert -- 2 Завершено left

    Need a Verilog expert with knowledge of ALtera Quartus and pipeining.

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    1. You have to teach us about RISC-V microcontroller architecture top to bottom and instructions . 2. You have to teach us about VHDL / VERILOG. 3. You can deal it with logisim software. 4. You have to give support and help us to build RISC-V microcontroller in FPGA. 5. You can take class about these minimum 2 days in online. 6. You will get 4 month to complete this. You will get 150$ as payment as a teacher. Payment can't be increased cause we are student(cause it is our saving money :) )

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