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    2,624 rwender fpga asic design работ(-а,-ы) найдено, цены указаны в USD

    ! Нужно сделать SEO оптимизацию для интернет магазина где продаются Асики для майнинга. -- Информация о сайте WebSite: [войдите, чтобы посмотреть URL] Сайт создан на конструкторе satu.kz. Title Asic Mining в Казахстане – Купить asic для майнинга. Keywords asic, asic miner, купить асик, купить асик в казахстане, asic цена, asic miner купить, купить асик в астане, асик, майнинг, mine...

    $90 (Avg Bid)
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    Linux Другое или затрудняюсь ответить Конфигурация прошивки на asic Майнер s9. Перезборка ядра, отключение ограничения на скорость вращения вентиляторов, полное их отключение. Создание прошивки для первичного запуска.

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    I've designed some verilog code, though it isn't working as expected- seemingly as I don't have enough experience with the terminology of the language. The code monitors a +12V/-12V Squarewave line. An external system drops the +12V portion of the Squarewave to 9V, then 6V, and then 3V- so that the line oscillates between 12/-12, then 9/-12, then 6/-12, then 3/-12 (all in volts). W...

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    Development environment for Opal Kelly FPGA with Front panel SDK 5 дней(-я) left
    ПОДТВЕРЖДЕН

    I want to learn and work on Opal kelly FPGA XEM6010-LX45. For this, I need a development environment to program on FPGA using Front panel SDK. I have this FPGA Board Deliverables: Need a detailed document for the below requirement 1. How to program on to the Opal Kelly XEM6010-LX45 FPGA from Front panel SDK 2. Linking Microsoft visual studio with wxwidgets for C# coding 3. Development steps for th...

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    I am using Altera DE2-115 FPGA board to configure it using Quartus software 17 lite edition. We have to use QSYS to assign addresses and link the processor, then assign inputs and outputs in VHDL and pin planner in Quartus, and then use NIOS II processor for Eclipse to write a program in C and run the board. I am seeking some help in building this mini thing. I am attaching a pdf file for the tas...

    $22 / hr (Avg Bid)
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    14 ставки

    I need a verilog code that create a 16 bit "Calculator" that uses the slide switches as binary input, and uses the push-button cross as action triggers. The accumulator value should be displayed on the seven segment display in hexadecimal. the center button should be clear, and the four buttons should be ADD, SUBTRACT, AND and XOR.

    $27 (Avg Bid)
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    5 ставки
    Bitcoin mining tweaks 3 дней(-я) left

    I have an idea for mining Bitcoin "smarter" and i need some help in code development and/or mining setup and understanding. To give you a brief description of the idea without getting into details at this stage: I will be mining solo using multiple ASIC miners and potentially some Cloud mining using GPU (i understand that solo mining is not profitable even with ASIC miners) but i have a...

    $20 / hr (Avg Bid)
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    6 ставки
    $23 / hr Ср. ставка
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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

    $95 (Avg Bid)
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    Dyumnin Semiconductors is in the ASIC/FPGA design business. We are looking for experienced PCB designers who can take our design sketches and convert it to functional PCB design. Please give references to past similar projects (FPGA+analog+high-speed) We are open for both hourly and fixed price contracts. Please provide your rate card for both in the bid document

    $27 / hr (Avg Bid)
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    13 ставки

    Implementation of Fractional order Integer/ Derivative Using GL algorithm based VHDL on FPGA. simple code which i need.

    $94 (Avg Bid)
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    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

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    12 ставки
    FPGA Communications project Заканчивающийся left

    We have a Quartus software license and two Arria 10 boards (Terasic Han Platform). We want to give video input to one of the FPGAs through USB-C port and transmit it to the other board with one or multiple serial lines. At the other board, we want to get this video as output from the USB-C port again. We have XTS-FMC Boards for connection between the two FPGAs. We need a highly experienced FPGA ...

    $1135 (Avg Bid)
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    About us All-in-one solution for market data, order interface, order management and risk controls – at FPGA network card Level. Support for multiple trading applications using a single interface to the exchange, yet providing individual view of the order books for each application. Many solutions that are currently available either crunch the speed tests or concentrate on functionality...

    $651 (Avg Bid)
    Местный
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    I am currently using Altera DE2-115 FPGA board to configure it using Quartus 17 lite edition software and write the code in VHDL. We have to use QSYS, and NIOS II for Eclipse to write a program in C and to run the board. I am seeking some help in building this mini thing.

    $27 (Avg Bid)
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    2 ставки
    FPGA DESIGN ENGINEER Завершено left

    We are seeking 1 FPGA Design Engineer for our new product development. FPGA Design Engineer Responsibilities: • Completing implementation in RTL • Ensuring robust and complete timing constraints • Optimizing FPGA code to balance performance, area, power, complexity and timing • Determining and executing development, integration, bring-up and test plans. • Working closely ...

    $37 / hr (Avg Bid)
    $37 / hr Ср. ставка
    25 ставки

    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

    $50 (Avg Bid)
    $50 Ср. ставка
    5 ставки
    FPGA Engineer Завершено left

    For a Software Defined Radio module we are looking for a senior FPGA engineer. - Process all received data - Filter data for results - Etcetera To process and filter the data on the modules and possible FPGA within a specific SDR device. You will work with persons out of our team. You solve and test the issues they implement. Budget $800

    $969 (Avg Bid)
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    BladeRF (Software Defined Radio) Завершено left

    BladeRF specialist is needed that has experience with SDR (Software Defined Radio). We would like to set certain functions in the BladeRF: - Receiver (capture data) - Transmitter (page request) - Process all received data - Filter data for results - Multi bands simultaneously - Software define directional radio/antennas - Software define reach/width radio/antennas - Etcetera Require solution to ...

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    Eye pupil tracking Завершено left

    I would like to do project in human eye pupil tracking system for video sequence using Verilog in Xilinx spartan 6 FPGA. Here with attached my equirements Requirements: 1. Find the pupil center coordinates and radius for various eye's. 2. Coordinates should be constant intervals while tracking. 3. Only video sequence to be used.... Not for image. Kindly send me possibility of above …...

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    Program a project Завершено left

    I am a worker for a software company. I am currently using Altera DE2-115 FPGA board to configure it using Quartus software. We have to use NIOS II processor, QSYS, and Eclipse to write a program and to run the board. I am seeking some help in building this mini thing.

    $17 / hr (Avg Bid)
    $17 / hr Ср. ставка
    14 ставки
    implementing 8-bit comparator Завершено left

    i need a 8-bit comparator characterizing overdrive, to be implemented on FPGA, using Verilog also I need the constrains file

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    FPGA Board Expert Завершено left

    An expert on FPGA Board should bid only, showing a sample work will be an advantages

    $235 (Avg Bid)
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    8 ставки
    Electronic engineer required Завершено left

    I am looking for electronic engineers having expertise in different microcontrollers like FPGA, Raspberry Pi, Arduino, PIC, ESP and many others having expertise in programming. I will share details of projects in chat

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    FPGA/VHDL/Verilog Завершено left

    Looking for implementation of a Ethernet Tester, generating and analyzing Ethernet traffic at 1G and 10G. More details on PM. J

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    We need to develop a digital multiplier circuit and we need to test the circuit design, Implement it in software environment and simulate the circuit functionality. This is going to be part of a bigger project (ARM IP Core, DSP CPU) and we may need to compare the circuit functionality with some other recommended multiplier in terms of speed and foot print.

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    mining software fpga Завершено left

    we need expierenced partner to build fpga mining software

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    Please read carefully. You need to fix my code. I will sent to you in messages my project. Here is project description: The brightness measurement with help of PMODALS sensor ([войдите, чтобы посмотреть URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([войдите, чтобы посмотреть URL]) is to be used, which takes over the...

    $522 (Avg Bid)
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    FPGA Board Завершено left

    An expert on FPGA Board should bid only, showing a sample work will be an advantages

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    12 ставки
    Fpga labview programming Завершено left

    Need expert labview for fpga control of an instrument

    $50 / hr (Avg Bid)
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    5 ставки
    FPGA project Завершено left

    I am looking for FPGA expert..

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    GPS implementation Завершено left

    first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PCB of the board you have. U3 is ...

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    FPGA program in singapore Завершено left

    Im looking for personnel to work on FPGA program in Singapore ,must be able to read current program or create an new program as required .Any one interested please contact me

    $330 (Avg Bid)
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    build me a CMOS sensor Завершено left

    I need a line scan CMOS sensor (pixel size 14 micron X 200 microns) capable of line scan at a rate of 80KHz and output the data through ethernet to Xilinx FPGA.

    $523 (Avg Bid)
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    FPGA Electric Engineering Завершено left

    Hello, We are looking for a FPGA electric engineer who can help us engineer a FPGA board, customize an existing board. Preferable who can also develop in Python and C to connect the FPGA board with a RaspberryPi, and develop programs on both boards. You will receive project information later.

    $1154 (Avg Bid)
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    Project for Rajagopal S. Завершено left

    Hi Rajagopal S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. The brightness measurement with help of PMODALS sensor ([войдите, чтобы посмотреть URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([войдите, чтобы посмотреть URL]) is to be used, which takes over the ...

    $221 (Avg Bid)
    $221 Ср. ставка
    1 ставки
    FPGA unit phasor measurements Завершено left

    First task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop The second part of the project task is to populate the ADC and final amplifier stages on the PMU PCB, together with power...

    $200 (Avg Bid)
    $200 Ср. ставка
    4 ставки
    Research help -- 3 Завершено left

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

    $316 (Avg Bid)
    $316 Ср. ставка
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    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

    $33 / hr (Avg Bid)
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    1 ставки
    customization of an SDR Завершено left

    We are looking at scanning,capturing and decoding multiple cellular frequencies(European 2G/3G/4G(LTE) bands) with an SDR. Currently using a simple rtl-sdr for this case but seeing as it lacks the frequency range(max 1800mhz) and has very little bandwidth(2.4MHz) we would like to upgrade to a better SDR. The goal is to analyze multiple simultaneous communication channels in real time. We are loo...

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    Freelancers from Australia only (preferred) Looking for a Chartered Accountant / CPAs (Mandatory) from Australia to conduct a training session for my team on AUS GST filing, ATO Filing, ASIC filing, and Payroll. Initial 2 hours meeting. Can have a follow up meeting of another few hours. Please bid with Hourly cost.

    $25 / hr (Avg Bid)
    Местный
    $25 / hr Ср. ставка
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    PCB Design Завершено left

    Use the xtal oscillator board that I designed and that works together with the FPGA to read the GPS data and then synchronise the 40 MHZ Voltage controlled Xtal oscillator to the 1 second pulse produced by the GPS. I will provide more details on chat.

    $156 (Avg Bid)
    $156 Ср. ставка
    18 ставки
    FPGA expert needed Завершено left

    I am looking for an expert in FPGA, its not a simple task, only expert place bids. will share details in chat

    $20 (Avg Bid)
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    7 ставки

    Need someone who has the PLDa PCIe ipcore license for Xilinx Vivado to help compile a FPGA project. I'll give you the source code. You compile and give me the bit file and compiled project.

    $207 (Avg Bid)
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    The test program used for transmited data between DDR4 of FPGA and DDR4 of PC adopted windows 10 or win7 system via PCIe 3.0 x8. A tested result shows that the speed of PCIE3.0 *8 is over 7GB/s , which is tested by xilinx Kcu1500 FPGA board. However, the speed under win7 / win10 is only about 4.5-4.9GB/s. The minimum speed threshold should be 5.5 GB/s. And it will be helpful if the speed...

    $7915 (Avg Bid)
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    Need example code de-10 Завершено left

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    i have projects related to all of these micro-controllers: Raspberry Pi FPGA PIC microcontroller STM microcontroller so looking for experts who can assist me with these projects

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