Simple fpga vhdl verilog projectsработы

Фильтр

Мои последние поисковые запросы
Фильтровать по:
Бюджет
по
по
по
Тип
Навыки
Языки
    Статус работы
    4,049 simple fpga vhdl verilog projects работ(-а,-ы) найдено, цены указаны в USD

    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

    $23 (Avg Bid)
    $23 Ср. ставка
    4 ставки
    Single Core and Pipeline MIPS Verilog 5 дней(-я) left
    ПОДТВЕРЖДЕН

    -Tools:Altera Quartus,Modelsim and FPGA. -This Project is divided to two parts:- [войдите, чтобы посмотреть URL] and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x 32)

    $351 (Avg Bid)
    $351 Ср. ставка
    4 ставки

    Requiring experienced electronics engineer/embedded software developer to assist with further design and development of FPGA system for synchronised communication with ADC's and DAC. The system is to be used in a precision materials testing instrumentation design. The ADC's to be used are the AD7768 (x2) and the DAC is AD5790. The DAC is to operate

    $583 (Avg Bid)
    $583 Ср. ставка
    5 ставки

    matrix multiplication using strassenalg and karatsuba alg and carry select adder

    $47 (Avg Bid)
    $47 Ср. ставка
    5 ставки

    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting

    $15 / hr (Avg Bid)
    $15 / hr Ср. ставка
    10 ставки
    FPGA with server 1 день left

    create a web api connect to the fpga cyclone v (altera de10-standred) , then altera can response to hte request change connect some point with each other.

    $547 (Avg Bid)
    $547 Ср. ставка
    5 ставки
    FPGA Programming 1 день left

    FPGA designer that can code chips for different FPGA aspects

    $25 (Avg Bid)
    $25 Ср. ставка
    6 ставки
    FPGA testbench in Verilog for SDRAM controller using SDRAM model 22 часов(-а) left
    ПОДТВЕРЖДЕН

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    $104 (Avg Bid)
    $104 Ср. ставка
    4 ставки

    ...counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Basys3 FPGA development board. The FPGA used is a Xilinx Artix-7 FPGA (XC7A35T-1CPG236C). An asynchronous high-active reset shall be used to initialize the design (BTNC button on the Basys3 board). The whole design

    $49 (Avg Bid)
    $49 Ср. ставка
    9 ставки
    verilog counter Завершено left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

    $62 (Avg Bid)
    $62 Ср. ставка
    7 ставки
    VHDL and FPGA programming Завершено left

    Here projects are implemented in VHDL programming using Xilinx software. B.E/[войдите, чтобы посмотреть URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

    $131 (Avg Bid)
    $131 Ср. ставка
    5 ставки

    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [войдите, чтобы посмотреть URL] file.

    $28 (Avg Bid)
    $28 Ср. ставка
    9 ставки

    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $759 (Avg Bid)
    $759 Ср. ставка
    1 ставки

    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $189 - $567
    $189 - $567
    0 ставки
    Digital Design - VHDL Programm Завершено left

    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit

    $43 (Avg Bid)
    $43 Ср. ставка
    11 ставки
    VHDL - Programming Digital Design Завершено left

    ...this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the difference between the data type bit and the data type std_logic in VHDL? What is the difference between the data type bit_vector and the data type std_logic_vector in VHDL? What is the difference between VHDL signals and

    $29 (Avg Bid)
    $29 Ср. ставка
    11 ставки

    ... Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream

    $565 (Avg Bid)
    $565 Ср. ставка
    1 ставки

    Hi, I need a quick prototype of an Artix-7 fpga that makes a pcie to sd card controller (SD host controller/SD bus). Objective is to have a fpga card (working on pcie screamer) recognized as a SD/MMC card reader under windows, I need Windows to recognize/be able to install the windows built-in sd card drivers for the card. I don’t need it to actually

    $252 (Avg Bid)
    $252 Ср. ставка
    3 ставки
    FPGA Board Re-Evaluation Завершено left

    Hi Freelancers, I have a project I've been working on for the past 4 months- an Altera FPGA control system for a specific application. I’ve had the control system previously evaluated by an engineer, although there are aspects of the system I’d like to have double-checked prior to production. I’d like an Electrical Engineer to simply re-confirm my

    $24 / hr (Avg Bid)
    $24 / hr Ср. ставка
    5 ставки

    We want a service of Fpga card design and embedded software

    $1222 (Avg Bid)
    $1222 Ср. ставка
    15 ставки

    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

    $296 (Avg Bid)
    $296 Ср. ставка
    11 ставки

    You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin

    $192 (Avg Bid)
    $192 Ср. ставка
    5 ставки

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    $628 (Avg Bid)
    $628 Ср. ставка
    23 ставки

    I need a board that has HDMI input and output, and allows to overlay some picture on the top of the HDMI video stream. The p...example). Basically On-Screen display for HDMI. Need PCB to be designed and a prototype built. Important: please let me know how would you approach this problem, would you use FPGA or some type of ASIC, which part number etc.

    $728 (Avg Bid)
    $728 Ср. ставка
    8 ставки
    FPGA and CMOS technology Завершено left

    FPGA and CMOS technology questions Just a few hours task Bit at hourly rate

    $1 / hr (Avg Bid)
    $1 / hr Ср. ставка
    1 ставки
    Altera DE2-115 small project Завершено left

    Hi, Looking to make a small communication interface on FPGA board, Altera DE2-115. Not to lengthy task, just a 4 signal interface. Use Quartus. Communication interface name, XY2-100 Max time, 3 days.

    $34 (Avg Bid)
    $34 Ср. ставка
    2 ставки
    Project for Ahmed M. Завершено left

    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. HI there, wondering if you ha...profile and would like to offer you my project. We can discuss any details over chat. HI there, wondering if you have the ability to create a bitstream for the XILINX VCU 1525 FPGA to mine cryptocurrency.

    $500 (Avg Bid)
    $500 Ср. ставка
    1 ставки
    Vivado Expert Завершено left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

    $27 / hr (Avg Bid)
    $27 / hr Ср. ставка
    9 ставки
    Project for JCSoft Завершено left

    Hello.. interested in a bitstream / miner for vu9p fpga card - VCU1525 -- let me know how much and if you can target equihash 150,5

    $30 / hr (Avg Bid)
    $30 / hr Ср. ставка
    1 ставки
    Embedded Software Project Team Завершено left

    Hi I am looking to offload a embedded system project which requires deep understanding of a) Hardware board design b) FPGA/RTL Developer c) Linux device driver expert d) software expert e) Signal processing expert

    $38932 (Avg Bid)
    $38932 Ср. ставка
    13 ставки

    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

    $115 (Avg Bid)
    $115 Ср. ставка
    3 ставки

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $1689 (Avg Bid)
    $1689 Ср. ставка
    8 ставки
    RISC-V and processors designing Завершено left

    ...REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture WE PREFER: - Experience with HW synthesis tools for ASIC/FPGA - Knowledge of versioning tools (Git, SVN) - Ability

    $1282 (Avg Bid)
    $1282 Ср. ставка
    13 ставки
    Processor design using Verilog Завершено left

    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

    $108 (Avg Bid)
    $108 Ср. ставка
    6 ставки

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $750 (Avg Bid)
    $750 Ср. ставка
    1 ставки

    ...chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further

    $776 (Avg Bid)
    $776 Ср. ставка
    9 ставки

    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

    $267 (Avg Bid)
    $267 Ср. ставка
    6 ставки

    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

    $1400 (Avg Bid)
    $1400 Ср. ставка
    14 ставки

    ...different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements, specs of FPGA, plan and ...

    $16 / hr (Avg Bid)
    $16 / hr Ср. ставка
    11 ставки
    Lattice Ice40 FPGA coding Завершено left

    Looking for an experienced programmer in Lattice FPGA's, specifically the ICE40 series. Simple project, buffer 320 bytes of data with multiple clock domains. Prefer VHDL

    $91 (Avg Bid)
    $91 Ср. ставка
    7 ставки
    Bitstream development for FPGA Завершено left

    I need you to develop Grin coin bitstream and provide miner compatible with BCU1525 FPGA.

    $555 (Avg Bid)
    $555 Ср. ставка
    1 ставки
    Need VHDL expert Завершено left

    I have a VHDL code. Then It has some issue. I need to fix it within a few hours. If you are electronic expert you can do it within 1 hours. I'll send details via interviewing. Ivan.

    $56 (Avg Bid)
    $56 Ср. ставка
    10 ставки
    VHDL or Verilog program Завершено left

    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

    $18 (Avg Bid)
    $18 Ср. ставка
    1 ставки

    I got DE2 115 FPGA board and to implement the LOW pass filter using MATLAB simulink.

    $27 (Avg Bid)
    $27 Ср. ставка
    6 ставки
    Bitstream Algo FPGA Завершено left

    I need you to develop bitstream algo (FPGA) for me. I would like this as soon as possible.

    $2726 (Avg Bid)
    $2726 Ср. ставка
    12 ставки

    I need to convert a python code to vhdl code using myhdl.i will attach the python code.

    $23 (Avg Bid)
    $23 Ср. ставка
    2 ставки

    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with reasonable

    $4254 (Avg Bid)
    Соглашение о неразглашении
    $4254 Ср. ставка
    12 ставки

    I have project with FPGA, need to read FPGA data which is driving LCD, after need to switch that data into VGA

    $1000 (Avg Bid)
    $1000 Ср. ставка
    1 ставки
    Altera FPGA Board Evaluation Завершено left

    Hi Freelancers, I have a project I've been working on for the past 2 months- an Altera FPGA control system for a specific application. Although I have knowledge in electrical engineering, I have no qualifications in the field, and thus I’d like a qualified individual to confirm my design, correct any mistakes I may have made, and possibly make the product

    $180 (Avg Bid)
    $180 Ср. ставка
    2 ставки