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    1,972 verilog projects spartan работ(-а,-ы) найдено, цены указаны в USD

    ...эти материалы. 3. Сайт должен уметь обрабатывать флэш 4. Сайт должен уметь нормально отображаться в разных версиях основных браузеров: Mozilla Firefox, Internet Explorer, Spartan, Safari, Opera 5. Сайт должен выдерживать нагрузку в 100 тысяч посещений в день. 6. Сайт должен иметь личный кабинет. Должна быть форма регистрации. 7. Сайт должен содержать

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    FPGA testbench in Verilog for SDRAM controller using SDRAM model 6 дней(-я) left
    ПОДТВЕРЖДЕН

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

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    Single Core and Five Stage Pipelined MIPS using Verilog 4 дней(-я) left
    ПОДТВЕРЖДЕН

    ...-Programming Language : Verilog HDL. -This project is divided to two parts:- Part 1. Design and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x

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    Artist for logo image 4 дней(-я) left

    ...warrior legends (geared at traveling salespeople), so I am looking for an illustration of a man in a business suit, well built but not a bodybuilder, with some sort of warrior/spartan helmet on, holding a briefcase, in the pose shown in the attached file (superman). I'd like the character to be backlit, not too much detail (simpler the better actually).

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    verilog counter 4 дней(-я) left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

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    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [войдите, чтобы посмотреть URL] file.

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $753 (Avg Bid)
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    1 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $189 - $567
    $189 - $567
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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $565 (Avg Bid)
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    1 ставки

    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

    $296 (Avg Bid)
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    11 ставки

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

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    Vivado Expert Завершено left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

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    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $1689 (Avg Bid)
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    RISC-V and processors designing Завершено left

    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

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    Processor design using Verilog Завершено left

    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $750 (Avg Bid)
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    ...Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further requirements (some

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    - Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements

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    ...to use any other images or graphics that you want. Be Creative and Have Fun with It! The colors are: Blue : 23456b Gold : f2a838 Gray : d9d9d9 The font family is: League Spartan I would like to get the editable file, especially if you are using Adobe products so that I can edit any text that you put in or if I need to move some graphics around. Let

    $25 (Avg Bid)
    Гарантированный
    VHDL or Verilog program Завершено left

    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

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    I need to convert a python code to vhdl code using myhdl.i will attach the python code.

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    Trophy icon Logo Designer/ Mascot Designer 4 дней(-я) left

    ...the body as the middle portion, and the tail as the bottom portion. In his right hand he will be carrying a spear which will run strait across 180 degrees, and in his left a Spartan-like shield with a very basic depiction of an ant with roman numerals around it (top view with its head toward the top of the shield). The reason for the ant is because myrmidon

    $100 (Avg Bid)
    Гарантированный

    ...Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

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    verilog / VHDL or FPGA expert only Завершено left

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

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    Carikan saya Marketing Freelance Завершено left

    Dibutuhkan seorang marketing freelance untuk menjadi Sole Agen di perusahaan kami PT. SPARTAN MULTI DISTRINDO, dengan kualifikasi : 1. Pengalaman marketing memasarkan produk alat kesehatan ke rumah sakit selama 3 tahun, 2. Memiliki data base rumah sakit di jawa barat, tangerang raya dan provinsi banten, 3. Punya kendaraan pribadi mobil atau motor, 4

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    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [войдите, чтобы посмотреть URL]; a. The source can

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    find fpga projects Завершено left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

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    Matlab Codnig Завершено left

    I need the matlab developer and verilog developer

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    Trophy icon Need a simple logo created. Завершено left

    I’ve provided 3 images found online to give an idea of what I’m looking for. First image is with the punisher in crosshairs. Replace punisher logo with a customized Spartan helmet (black) within the crosshairs (red). Customize it to be distinctive and allow for trademarking. Add the letters “TSG” in the helmet somewhere. I may add text around the circle

    $20 (Avg Bid)
    16-point FFT Завершено left

    verilog code for radix-4 16 point fft

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    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $11834 (Avg Bid)
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    2 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $10690 (Avg Bid)
    $10690 Ср. ставка
    1 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

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    Trophy icon Logo Design Завершено left

    I need a Logo...Laser/embroider on stuff. Also nothing with Weapons in the logo since it shouldn't be too revealing what the Company is about. Several ideas: -Only a logo with the letter "V" -A spartan Helmet with the letter "V" ( attached picture for reference) -A Shield with three parts for the three branches of the company -Not too many colors

    $50 (Avg Bid)
    Гарантированный Скрытый

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $882 - $882
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    0 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $884 - $884
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    0 ставки

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $933 (Avg Bid)
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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $736 - $883
    $736 - $883
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    reviewing a code Завершено left

    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

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    CS 223 Digital Design: Smart Evacuation Elevator (System Verilog) Ödevin 21 Aralık 2018'e yetişmesi gerekiyor. Ödev hakkında bilgi için lütfen iletişime geçiniz.

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    LUT optimization of FFT Завершено left

    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

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    Verilog Expert Завершено left

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

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    Design 4 bit Adder in Verilog Завершено left

    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

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    Logo Design project Завершено left

    We want a logo for apparel and brand purposes. We would like something spartan related (Spartan Helmet, Spear, Shield).

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    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

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    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

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    7 ставки