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    1,933 verilog projects spartan работ(-а,-ы) найдено, цены указаны в USD

    ...эти материалы. 3. Сайт должен уметь обрабатывать флэш 4. Сайт должен уметь нормально отображаться в разных версиях основных браузеров: Mozilla Firefox, Internet Explorer, Spartan, Safari, Opera 5. Сайт должен выдерживать нагрузку в 100 тысяч посещений в день. 6. Сайт должен иметь личный кабинет. Должна быть форма регистрации. 7. Сайт должен содержать

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    LUT optimization of FFT 6 дней(-я) left

    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

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    Verilog Expert 5 дней(-я) left
    ПОДТВЕРЖДЕН

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

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    Design 4 bit Adder in Verilog 5 дней(-я) left

    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

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    Logo Design project 2 дней(-я) left

    We want a logo for apparel and brand purposes. We would like something spartan related (Spartan Helmet, Spear, Shield).

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    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

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    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

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    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    How does...be increased as well as showing that i am authorized to park only at level 2 and there is only for example 7 vacant lots for staff in level 2. The system is : FPGA ;Nexys 2 spartan 3E, Camera connected to the FPGA, And the monitor connected via VGA to the FPGA, The gates(pairs of IR sensors) in a bread board as illustrated in the abstract.

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    FPGA Verilog Programming Завершено left

    Need help program FPGA with Artix-7 using Verliog.

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    Urgent FPGA Verilog Project Help Завершено left

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

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    Zen Protocol Miner in Verilog/VHDL Завершено left

    Implement the Zen Protocol in the FPGA and update the Mining App

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    ...but you also have to write the result to the $rd register as R-type instructions require. Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed except for the register module. This means you cannot use assign, ifelse, always, ?: and etc

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    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions

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    Make a serial interface system using Verilog

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    ...but you also have to write the result to the $rd register as R-type instructions require. Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed except for the register module. This means you cannot use assign, ifelse, always, ?: and etc

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    Solving FPGA output module Завершено left

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

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    Solving FPGA output module Завершено left

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

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    Trophy icon Design a Logo Завершено left

    Simple Project Need Spartan Head with words [войдите, чтобы посмотреть URL] XXIII Catholic Elementary School. PDF FILE IN WHITE

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    Design of a signal generator using verilog hdl. Should be done using Vivado Design Suite . More details in chat.

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    Video Compression Using FPGA Завершено left

    ...can burn the image to my fpga and simply voila.. Kindly visit this link in order to get an insight to the board that I will be using… [войдите, чтобы посмотреть URL] I want video to be input from HDMI in port on the board and output ( a compressed video) via HDMIout port on the FPGA

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    Trophy icon Logo Design Завершено left

    Security Company. Armed, Physical Security. Company name is "Aspis Defense Group". Aspis refers to a shield used by ancient...Armed, Physical Security. Company name is "Aspis Defense Group". Aspis refers to a shield used by ancient Greek infantry (Spartans primarily). Looking for something spartan related, spartan shield (round), ancient Greek themed.

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    image water marking Завершено left

    image watermarking baed on dct algorithm in verilog code, need to implement in xilinx board

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    Part 1: Dynamic Patterns Using LEDs Requirement In this part, you are required to write a Verilog code that produces at least four different dynamic patterns, that is changing with time with reasonable speed. And those patterns are controlled by switches. Features • Use the most left switches to change the patterns. • Design your own patterns. • Use

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    Verilog game Завершено left

    I have a verilog game. I need a freelancer to change the resolution of the game and add a background.

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    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

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    Verilog Ethernet protocol Завершено left

    I want to implement the Ethernet connection. The deliverables are as follows -Verilog code to run on a Spartan 6 Board - (xc6slx100) -simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 1000mbs.

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    Simple project, that basically should detail the observed waveforms and max frequency of given code.

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    Project for Behailu D. Завершено left

    Hi Behailu D., I noticed your profile and would like to offer you my project. We can discuss any details over chat. conversion python to verilog

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    Programacion en Verilog -- 2 Завершено left

    El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su...

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    Programacion en Verilog Завершено left

    El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su...

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    Hey, I need a logo in a cartoonish style for a gaming community. It needs to have the spartan helmet as a main focus. I attached examples etc. Important: The spartan helmet should be viewed from the SIDE. Make a good font below it with following content: Header: Achilles Subheader: Multigaming Community I need Vector files. (Illustrator, Photoshop

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    Verilog Altera Cyclone 5 maze game Завершено left

    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

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    8-bit Calculator Завершено left

    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

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    Verilog board mini game Завершено left

    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

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    Matlab to Verilog Завершено left

    Code needs to be ported from Matlab to Verilog

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    Trophy icon New Logo 2018-1 Завершено left

    We are a consulting company working on a number of projects from Capital raising, property development to Manufacturing, etc. We are in need of a new Logo that incorporates the following: The name: Titan Consultancy, Spartan War Helmet. Incorporate the Greek Key Symbol. The logo will also need to be part of a Signature for email and for letterhead

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    Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

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    ...with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note: Please attach any necessary files with a brief description of the

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    Thunderbird Turn Signal Завершено left

    1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA

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    upgrade electronic PCB board Завершено left

    Hi ! I currently need pcb layout engineer to upgrade my personal fpga board. It previously used Spartan 3E FPGA PQFP (PQ208/PQG208) package using the power voltage of 3.3v, 2.5v, 1.2v ... I'd like to have it replaced by an Artix fpga (FG484/FGG484 Fine-Pitch BGA package), henceforth using the lower voltages of 3.3v, 1.8v, 1.0v The voltage regulators

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    Verilog Task with Icarus Verilog Завершено left

    ALU Design as per instructions in Verilog Task . Simulation done using Icarus VERILOG

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    ...build a app that is a prefect blend between these two apps. I want all the workout features and layout of the ThenX app with the ability to have some of the features that the spartan app offers. I want to be able to white label this app and sell to others that might be looking for a similar style app. I want it to be easy to upload custom videos that

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    I need VLSI design video tutorials Завершено left

    I need someone to create video tutorials for VLSI design from basics to advanced concepts. Advanced Digital Design Concepts CMOS Logic fundamentals RTL Design with Verilog HDL's ASIC Design Systhesis Concepts ASIC Design Stratagies Static Timing Analysis Low power design implementation Design and power Constraints Perl/Shell Scripting EDA tools usage

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    Need someone who has the tools and/or ability to convert a relatively simple verilog (.v) file to liberty timing (.lib) format, and who can verify the resulting .lib file. If successful and painless, there will be more such projects.

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