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    1,355 verilog projects работ(-а,-ы) найдено, цены указаны в USD
    $23 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    18 ставки

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [войдите, чтобы посмотреть URL]

    $46 (Avg Bid)
    $46 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    16 ставки

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    $23 (Avg Bid)
    $23 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    22 ставки
    Simple Verilog Program. Завершено left

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    $22 (Avg Bid)
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    17 ставки
    Verilog design project Завершено left

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    $21 / hr (Avg Bid)
    $21 / hr \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    20 ставки
    Verilog program counter Завершено left

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    $131 (Avg Bid)
    $131 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    19 ставки

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
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    13 ставки
    System Verilog Trainer Завершено left

    We are looking for a System Verilog Training for few Engineers in our premises.

    $1983 (Avg Bid)
    $1983 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    5 ставки

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    $100 (Avg Bid)
    $100 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    8 ставки
    System Verilog Project 5 Завершено left

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $121 (Avg Bid)
    $121 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    21 ставки
    Alarm clock Verilog Завершено left

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $184 (Avg Bid)
    $184 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    15 ставки

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
    $86 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    5 ставки
    Verilog Coding expert needed Завершено left

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $106 (Avg Bid)
    $106 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    11 ставки
    Convert a python program to vhdl Завершено left

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $132 (Avg Bid)
    $132 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    7 ставки

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [войдите, чтобы посмотреть URL] Using PG236 [войдите, чтобы посмотреть URL]

    $128 (Avg Bid)
    $128 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    3 ставки

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    $72 (Avg Bid)
    $72 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    1 ставки
    Project for Iqra Software .. Завершено left

    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    $42 / hr (Avg Bid)
    $42 / hr \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    1 ставки
    Image encryption Завершено left

    I need image encryption using verilog on FPGA board

    $803 (Avg Bid)
    $803 \u0421\u0440. \u0441\u0442\u0430\u0432\u043a\u0430
    13 ставки

    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

    $29 (Avg Bid)
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    16 ставки
    Reed solomon encoder and decoder Завершено left

    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

    $563 (Avg Bid)
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    11 ставки