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    3,016 verilog vhdl работ(-а,-ы) найдено, цены указаны в USD

    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

    $23 (Avg Bid)
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    4 ставки
    Wristwatch-VHDL -- 2 6 дней(-я) left

    Design a multifunction wristwatch that has time-keeping, alarm, and stopwatch functions. The wristwatch has three buttons (B1, B2, and B3) that are used to change the mode, set the time, set the alarm, start and stop the stopwatch, and so on. Pushing button B1 changes the mode from Time to Alarm to Stopwatch and back to Time. The functions of other buttons vary depending on the mode.

    $42 (Avg Bid)
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    2 ставки
    Wristwatch-VHDL 5 дней(-я) left

    Design a multifunction wristwatch that has time-keeping, alarm, and stopwatch functions. The wristwatch has three buttons (B1, B2, and B3) that are used to change the mode, set the time, set the alarm, start and stop the stopwatch, and so on. Pushing button B1 changes the mode from Time to Alarm to Stopwatch and back to Time. The functions of other buttons vary depending on the mode.

    $27 (Avg Bid)
    $27 Ср. ставка
    3 ставки
    DICE GAME in VhDL 4 дней(-я) left

    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [войдите, чтобы посмотреть URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 t...

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    ...document it. Project is already split and documented as 10 milestones so that development can be done incrementally, step by step, and reviewed/monitored. Project is mostly Verilog development. Some simple programming necessary as well. Documentation is required. We expect you to reserve 10-20 hours per week for this project. It should be around 80 hours

    $12 / hr (Avg Bid)
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    I need single cycle 32 bit mips vhdl coding to find prime numbers. I will provide code to find prime number so you just have to build cpu for this specific purpose and I am also going to provide parameters for this architecture. I am gonna share project file after finalising with best person to do this job

    $111 (Avg Bid)
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    2 ставки

    We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado. There are 5 blocks in total with the following functionalities: 1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench. 2. RDM Memory: Write a wrapper for the Xilinx

    $497 (Avg Bid)
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    12 ставки

    I'm a electronic engineer and I have a good command on computer programs and also on digital programming like VHDL.

    $21 / hr (Avg Bid)
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    1 ставки
    Need help regarding FPGA and VHDL 3 дней(-я) left
    ПОДТВЕРЖДЕН

    You have to write code and report for this .

    $21 (Avg Bid)
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    13 ставки

    In this project, you are required to develop a structura...upload to the PC for display. Verify the results by comparing them with another method (e.g., C program, spreadsheet etc.). This project Must be built using Quartus Prime's Verilog code. A code example is attached, you can follow the example but please modify it to fit my project description.

    $125 (Avg Bid)
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    4 ставки

    I have the scheme of the project need only to work with the basys 3. Only to use buttons and switches from the basys3. Need the whole code in VHDL for Vivado.

    $21 (Avg Bid)
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    Develop a 32‐bit single or multi‐cycle CPU capable of performing a search for prime numbers.    CPU

    $134 (Avg Bid)
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    4 ставки
    FPGA Content Writer 4 часов(-а) left
    ПОДТВЕРЖДЕН

    ...documentation related to Xilinx and Verilog development as well as custom hardware accelerators. Content is in the form of educational papers for semi-technical audience. Each article/paper is expected to be around 1900 words (4-5 pages, plus custom diagrams/infographics). Candidates must be able to prove experience in RTL/Verilog/FPGA development as well as

    $130 (Avg Bid)
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    13 ставки
    Create VHDL chess clock Завершено left

    Has to be completed by the end of tomorrow (13/05/2019) Create VHDL code for chess clock, uploaded the task as a file.

    $123 (Avg Bid)
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    3 ставки
    embedded systems engineer required Завершено left

    freelancer required for small project. must know FPGA programming/VHDL/Verilog

    $25 (Avg Bid)
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    4 ставки

    Some work related to fpga and vhdl. Need any expert who can manage that

    $21 (Avg Bid)
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    3 ставки

    I have 2 schemes. One with neuron and with genetic algorithm. I need to combine both to train this neuron via genetic algo. Using VHDL in ISE design suite 14.7. Here is [войдите, чтобы посмотреть URL] picture of two symbols that I want to combine(gen - genetic algorithm with build in neuron process, neur4sigm - neuron with sigmoid func). I need to train this neuron with

    $149 (Avg Bid)
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    5 ставки
    Nexys 4 Artix-7 Accelerometer Завершено left

    Want to be able to use accelerometer data on microblaze softcore processor, need SPI driver and interface on VHDL

    $221 (Avg Bid)
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    2 ставки
    Electrical Engineering VHDL Task Завершено left

    Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from an electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relationship with the perfect electrical engineering freelancer. Thanks.

    $158 (Avg Bid)
    $158 Ср. ставка
    7 ставки
    Artix-7 DDR FPGA Accelerometer Завершено left

    Hello, I'm currently working on a project that I am struggling with due to lack of VHDL experience. Want to create an SPI driver and interface it with a Microblaze softcore processor and the on-board accelerometer (ADXL362) so that the processor can read the accelerometer data.

    $257 (Avg Bid)
    $257 Ср. ставка
    14 ставки
    System Verilog FPGA project Завершено left

    Write system verilog codes to build a dual thread core processor working using Tomasulo algorithm. Please view the attached PDF for detailed information.

    $126 (Avg Bid)
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    8 ставки
    VHDL Assignment Завершено left

    I need you to develop some VHDL software for me. Message for further details

    $158 (Avg Bid)
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    15 ставки
    VHDL project Завершено left

    I need you to develop some VHDL software for me. Contact me for more details

    $211 (Avg Bid)
    $211 Ср. ставка
    6 ставки
    VHDL tasks Завершено left

    I have some simple VHDL tasks. My deadline is tomorrow. 1. Suggest a structural and behavioral description of a bidirectional cyclic shift register. 2. Suggest a structural and behavioral description of a bidirectional arithmetic shift register. Use parallel generation operators and configuration options. 3. Create a subroutine that performs the conversion

    $26 (Avg Bid)
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    4 ставки
    $110 Ср. ставка
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    $16 Ср. ставка
    7 ставки

    Design Verilog 32 bit adder, and use that to implement multiply using Xilinx

    $101 (Avg Bid)
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    2 ставки
    Design Record Portfolio Завершено left

    VHDL and FPGA system using vivado program.

    $654 (Avg Bid)
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    7 ставки
    VHDL software Завершено left

    I need you to develop some VHDL software for me. Must have good VHDL background. Message me for more details. Thank You.

    $44 (Avg Bid)
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    5 ставки
    Vhdl programer Завершено left

    I need a vhdl task done along with report

    $30 (Avg Bid)
    $30 Ср. ставка
    7 ставки

    Looking for a Vivado Studio Specialist to evaluate code. On a Zturn board ( Xilinx Soc 7000 Series.) Skills required: AXI RTL Vhdl Vivado Studio

    $134 (Avg Bid)
    $134 Ср. ставка
    3 ставки
    Need help related to fpga and Vhdl Завершено left

    You have to complete coding and report writing

    $67 (Avg Bid)
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    5 ставки
    FPGA verilog UART Завершено left

    I want the verilog UART code along with pin assignment, synthesis and waveform outputs using Quartus II tool on ALTERA DE2 Board.

    $48 (Avg Bid)
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    3 ставки

    I need a block to select some outputs based on the input and previous values of the input in VHDL

    $30 (Avg Bid)
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    6 ставки
    VHDL Electrical Engineering Task Завершено left

    Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relation with the perfect electrical engineering freelancer. I need to hire 3 freelancers for 3 copies of the task. Thanks

    $126 (Avg Bid)
    $126 Ср. ставка
    7 ставки
    I need a random number generator Завершено left

    I need a random number generator which will work on a fpga board and the code should be written in xilinx, should be a vhdl code

    $27 (Avg Bid)
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    11 ставки
    Get data to an FPGA Завершено left

    I have the Deo Nano Soc and I want to read data using DMA. I need to read at a rate of about 2MB/s. I have used VHDL for a while and if you could provide some protocol/instructions at the top level, I could do the rest.

    $127 (Avg Bid)
    $127 Ср. ставка
    6 ставки
    $90 Ср. ставка
    1 ставки
    VHDL Startup Завершено left

    Starting a small business programming registers, buttons, and switches on my FPGA board in VHDL. Looking to hire a programmer that knows basic/simple vhdl coding skills and can complete the startup within a few days preferably.

    $62 (Avg Bid)
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    9 ставки
    verolig calculator Завершено left

    A project to implement a calculator(ALU) in Verilog code using Quartus program I need a detailed report with state diagram and finite state machine I need one who can access my computer to teach me how to do the settings of the program also the Verilog code will be implemented on ALTERA board(DE2-115) also I need instructions of how I can run on

    $56 (Avg Bid)
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    7 ставки
    Microprocessor using verilog Завершено left

    Microprocessor design project using system verilog in Modelsim and physical validation on Quartus Prime. I have started writing code for some of the blocks. The Register file, ALU and Instruction memory are nearly complete. Assistance needed in writing the remainder of the blocks: the instruction register, the micro controller unit, the W register,

    $139 (Avg Bid)
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    5 ставки
    VHDL, FPGA, VGA Завершено left

    Hi I'm looking for a good vhdl programmer to help me with a code. I'm supposed to bring in a simple logo, then i,m supposed to be able to display the logo on the center of a screen(using a vga connection) and my name on the bottom left corner while being able to flip the logo with a button on my fpga board the deadline is thursday. thank you. I have

    $64 (Avg Bid)
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    Matlab to Verilog Conversion Завершено left

    We are working on an FPGA based doppler flowmeter with a custom PCB. At the moment, we are in the process of modeling algorithms using raw data recording in Matlab. This freelancer will be tasked with coordinating with the DSP engineer to design and implement changes from the Matlab models into our custom PCB, which Cyclone IV based. There is an existing version of both the recording firmware and ...

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    9 ставки
    $244 Ср. ставка
    3 ставки

    I have a digital input measurement signal, 0 ~...ZCU102 PL side RTL and bit file, Petalinux Image and drivers. 3. Remote support, to set up the whole system. 4. A block diagram and a brief explanation about your RTL code. Verilog is preferred. Please in the proposal, let me know how long would the project take and how much would you ask to build it.

    $1137 (Avg Bid)
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    4 ставки

    I need you to develop some software for me. I would like this software to be developed for Windows using Verilog/VHDL.

    $10 - $30
    $10 - $30
    0 ставки
    Verilog Alarm Clock Завершено left

    Create verilog code for an Alarm clock with testbenches. Alarm clock will display on 7 segment display. More information available upon request. Simple Project

    $155 (Avg Bid)
    $155 Ср. ставка
    1 ставки

    ...some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read enable from data

    $199 (Avg Bid)
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    5 ставки

    I am enclosing description in the files.

    $38 / hr (Avg Bid)
    $38 / hr Ср. ставка
    4 ставки
    Verilog Work required Завершено left

    Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.

    $29 (Avg Bid)
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    6 ставки