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    2,279 vhdl project vhdl project работ(-а,-ы) найдено, цены указаны в USD
    Project for Pavlo H. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. ставка
    1 ставки
    Project for Mykyta M. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. ставка
    1 ставки

    Имеется проект VHDL, необходимо процессы вынести в отдельные компоненты без потери функциональности и работоспособности тестбенча.

    $32 (Avg Bid)
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    2 ставки

    Разработка системы Формирования звуковых оповещений на основе FPGA,(Development of a system for generating sound notifications based on FPGA.)

    $38 (Avg Bid)
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    3 ставки
    Project for Sergey G. Завершено left

    Здравствуйте, Sergey G.! Я обратил внимание на ваш профиль и хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $35 (Avg Bid)
    $35 Ср. ставка
    1 ставки
    Project for Oleksandr S. Завершено left

    Здравствуйте, Clevermindolex! Хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $30 (Avg Bid)
    $30 Ср. ставка
    1 ставки

    Цветомузыка. Адресная светодиодная лента, фильтр по частотам (высокие, средние, низкие), в зависимости от громкости и частоты мигает лента разными цветами

    $17 (Avg Bid)
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    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

    $23 (Avg Bid)
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    4 ставки
    VHDL Coding 6 дней(-я) left
    ПОДТВЕРЖДЕН

    Looking for VHDL coding of the following: 200Mhz Clock Output of Digital signal as follows: 35ns High 50ns Low total time 85ns Stays low for 1us Repeat

    $28 (Avg Bid)
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    7 ставки

    If you have experience in VHDL and digital electronic. Please read the paper requirements. I look forward working with you. Thanks

    $16 / hr (Avg Bid)
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    14 ставки
    VHDL digital electronic 4 дней(-я) left

    You must have experience in writing VHDL code and in digital electronic.

    $18 / hr (Avg Bid)
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    8 ставки
    VHDL desingner 3 дней(-я) left

    I need a VHDL designer to do the work today eda play [войдите, чтобы посмотреть URL]

    $24 (Avg Bid)
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    6 ставки

    Design challenges – specific for combinational circuits (aimed at problem solving) 2. Design challenges including full VHDL implementation and display on the Nexys4 Board (aimed at enhancing programming skills)

    $36 (Avg Bid)
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    VHDL expert needed 7 часов(-а) left

    Design a serial communication protocol i.e., telegram containing data bus, address bus, read/write bus and checksum(CRC). 1. read/write access is to be transferred. If CPU is doing a write access, then it should have 1 byte address and 1 byte data and control bits if possible. 2. Read bus should read the address to be transferred. 3. The write bus should transfer the PSS signal or the chip select...

    $218 (Avg Bid)
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    9 ставки
    need FPGA expert to add a spi interface 6 часов(-а) left
    ПОДТВЕРЖДЕН

    I need you to debug a module in vhdl for me. I would like this to be developed quickly

    $32 (Avg Bid)
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    9 ставки

    Risolvere un esercizio di VHDL semplice in cui si utilizza sensori, timer e altri circuiti standard. Per maggiori informazioni contattatemi in messaggio privato. Massima serietà, molto importante la professionalità e conoscere bene il linguaggio di programmazione.

    $36 (Avg Bid)
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    1 ставки

    I have one zed board with ethernet on it. I one to display the output of the adder over the ethernet. Adder is not an issue you can download it from anywhere, should be in VHDL, then the output of the adder should be transferred to the ethernet and then use the telnet or putty to display the Output.

    $472 (Avg Bid)
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    5 ставки
    VHDL Expert needed -- 4 Завершено left

    communication between two usarts

    $111 (Avg Bid)
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    2 ставки
    VHDL implementation of UART Завершено left

    I need vhdl code for uart to be implemented on basys 3 my budget is 150 usd max

    $112 (Avg Bid)
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    15 ставки

    I need a VHDL code of LVDS transmission between two FPGA`s. It is a 4 lane LVDS operating at 833.33MHz to transfer information from USART of 1st FPGA to USART of 2nd FPGA.

    $71 (Avg Bid)
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    VHDL Expert needed Завершено left

    I need to write VHDL code for LVDS transmission between two FPGAs. Please ping me if you are familiar with this.

    $30 (Avg Bid)
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    3 ставки

    Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

    $50 (Avg Bid)
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    1 ставки
    VHDL compression and decompression Завершено left

    Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

    $12 / hr (Avg Bid)
    $12 / hr Ср. ставка
    2 ставки
    $21 Ср. ставка
    7 ставки

    Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

    $169 (Avg Bid)
    $169 Ср. ставка
    4 ставки
    Project for Nikita A. Завершено left

    Hi nikafanasnikafan, I noticed your profile and would like to offer you my project in VHDL. We can discuss any details over chat.

    $50 (Avg Bid)
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    1 ставки
    Lock In amplifier Завершено left

    I want to built a digital lock in amplifier. I prefer to use VHDL and spartan3E board for the project. it will give the depth idea of phase locked loop, direct digital synthesis.

    $79 (Avg Bid)
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    2 ставки
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    In this project, a simple VGA (Video Graphics Array) controller shall be implemented using an FPGA Basys3. You have to implement the game of pong. One palette should be operated by the user with the help of buttons, and the other should be controlled by the computer. To be able to view the score.

    $13 / hr (Avg Bid)
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    2 ставки

    big team required Coin expert+ VHDL developer+ FPGA expert at least a coin expert and VHDL developer

    $2812 (Avg Bid)
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    4 ставки
    Project for Shai K. Завершено left

    Hi, We need some helps with the VHDL code. We use CYC1000-with-Cyclone-10-FPGA do you have time?

    $301 (Avg Bid)
    $301 Ср. ставка
    1 ставки
    Project for Junaid A. Завершено left

    Hi, We need some helps with the VHDL code. We use CYC1000-with-Cyclone-10-FPGA do you have time?

    $303 (Avg Bid)
    $303 Ср. ставка
    1 ставки

    Looking for a developer willing to create bitstreams for FPGA crypto mining. Looking for a reliable dev with good experience. If you believe you fit the profile, pls apply. We are looking for serious candidates only.

    $500 (Avg Bid)
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    Xilinx FPGA-based implementation of the parameterized delay line with good resolution, say in steps of 10ps and good delay range say 512 steps and with minimum FPGA resources say less than 2% utilization. Deliverables 1. RTL code in Verilog/SV/VHDL and Xilinx Syntheis scripts 2. TB and Verification environment (with parameters) and results 3. Documentation with Architecture Diagram, Algorith...

    $424 (Avg Bid)
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    11 ставки

    Looking for a developer willing to create bitstreams for FPGA crypto mining. Looking for a reliable dev with good experience. If you believe you fit the profile, pls apply. We are looking for serious candidates only.

    $546 (Avg Bid)
    $546 Ср. ставка
    6 ставки
    ARM MicroProcessor programming Завершено left

    by using VHDL and software Modelsim i need code and simulation of ARM microprocessor architecture

    $152 (Avg Bid)
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    9 ставки
    Frame Buffer Завершено left

    Develop VHDL IPs for high speed read and write to DDR for image processing applications for NIOS based SoC designs

    $20 / hr (Avg Bid)
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    3 ставки
    Needed Matalb /HDL conder Expert Завершено left

    I'm looking for a FPGA Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The right candidate should have an experience in Matlab and HDL Coder. The board is Zynq FPGA controller. The project is to implemente a Xilinx partial reconfiguration model for an SDR on the AD9361-Z7035 with ADRV1CRR-BOB. Also should have telecommunication knowledge. Please bid with the ...

    $21 / hr (Avg Bid)
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    10 ставки

    I have a board with a Xilinx FPGA programmed in VHDL using Xilinx ISE Design Site 14.7 . The FPGA performs many functions on the board address decode frequency counting, totalizing, latch logic and quadrature decode etc. We need this part of the project debugged or rewritten. I want to know if you would like to accept this project on a fixed cost basis. If so I will share the project with you and...

    $250 (Avg Bid)
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    1 ставки
    Project for Majid A. Завершено left

    I have a board with a Xilinx FPGA programmed in VHDL using Xilinx ISE Design Site 14.7 . The FPGA performs many functions on the board address decode frequency counting, totalizing, latch logic and quadrature decode etc. We need this part of the project debugged or rewritten. I want to know if you would like to accept this project on a fixed cost basis. If so I will share the project with yo...

    $250 (Avg Bid)
    $250 Ср. ставка
    1 ставки
    Looking for VHDL expert Завершено left

    I would like to discuss details via chat

    $60 (Avg Bid)
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    12 ставки

    Looking for flexible people with experience in microprocessor, microcontroller, FPGA, VHDL, Assembly, Arduino, PCB layout, digital design subjects

    $22 (Avg Bid)
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    15 ставки

    I get HD SDI video from GTH pins in fpga. I write data in DDR4 and then i read again and convet to HD SDI video, i receive video but it has some problems. I need to help to solve it

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    I have full code working on MAX10M16D. The task is to optimize the VHDL code for 10M04. I am looking for VHDL coder who has experience hdl optimization.

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    Have a few equations which need to be implemented in system Verilog or uvm. It will have sine functions, signed numbers, etc. Have a reference model in VHDL

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    Design project on Verilog HDL Завершено left

    Hello there, I need someone who can design a project on Verilog HDL using Quartus II. Hardware not needed here. Those who are available and willing to do it, please make a bid. Don't change the prices differently in the bid and in conversation. Thank you. *It is only in Verilog HDL, not in vhdl.

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    3 ставки
    vhdl code review and improvement Завершено left

    Wrote some vhdl code and it simulates but I want to optimize it for synthesis. Should not take longer than hour or two.

    $51 (Avg Bid)
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    I need someone with extensive knowledge in Digital Systems Design and VHDL to help me explain a few concepts

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    Assalam o alaikum, I am looking for expert in assembly language and VHDL coding. I would prefer to work with pakistani freelancers.

    $176 (Avg Bid)
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