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    1,756 vhdl work freelancer работ(-а,-ы) найдено, цены указаны в USD

    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

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    matrix multiplication using strassenalg and karatsuba alg and carry select adder

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    ...or octal) and the counting frequency of the least significant digit (1 Hz, 10 Hz, 100 Hz, or 1000 Hz) depend on your number in the attendance list as shown in Table 1 (if you work in groups, use the number of the group member with the lowest number). All four digits of the counter have to count at the same clock edge, this has to be proven by simulation

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    Here projects are implemented in VHDL programming using Xilinx software. B.E/[войдите, чтобы посмотреть URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

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    Digital Design - VHDL Programm Завершено left

    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit

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    VHDL - Programming Digital Design Завершено left

    ...this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the difference between the data type bit and the data type std_logic in VHDL? What is the difference between the data type bit_vector and the data type std_logic_vector in VHDL? What is the difference between VHDL signals and

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    You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin

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    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    RISC-V and processors designing Завершено left

    ...looking for a new mate/co-worker who can detect problems quickly, learn new technologies fast, and participate in designing processors with enthusiasm. WE OFFER: - Opportunity to work with RISC-V, computer architecture of the future - Working on innovative IoT processors and unique processor optimization technology - Participation in the whole development

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    ...be provided + timing chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    Lattice Ice40 FPGA coding Завершено left

    Looking for an experienced programmer in Lattice FPGA's, specifically the ICE40 series. Simple project, buffer 320 bytes of data with multiple clock domains. Prefer VHDL

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    Need VHDL expert Завершено left

    I have a VHDL code. Then It has some issue. I need to fix it within a few hours. If you are electronic expert you can do it within 1 hours. I'll send details via interviewing. Ivan.

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    VHDL or Verilog program Завершено left

    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

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    I need to convert a python code to vhdl code using myhdl.i will attach the python code.

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    ...speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements Notes: 1- Espresso

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    Bug-fix/Update FPGA Miner Завершено left

    Bug-fix Mining App and FPGA-VHDL Project. You have to fix the mining App what is written in C and running on a Linux server. And fix on the FPGA side the PLL and add multicores.

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    I would like to implement a calculator which takes inputs from the ps2 keyboard and displays them on 7 segment.

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    Online Tutor Embedded C/C++ Завершено left

    Tutor/Mentor Required(Online): -- Good knowledge of Embedded c/c++ and VHDL -- Good Experience with Renesas Microcontrollers and e2 Studio

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    Multiplexer of 2 to 1 in vhdl Завершено left

    Muktiplexer of 2 to 1 in vhdl using tje software xillinix

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    verilog / VHDL or FPGA expert only Завершено left

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

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    ...develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [войдите, чтобы посмотреть URL]; a. The source can be taken as https://github

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    find fpga projects Завершено left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

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    Hi,eveyone.I need a signal processing coding for my work using altra quartus II and VHDL.

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    Соглашение о неразглашении
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    implementation of 4 bit alu Завершено left

    Implementation of 4 bit alu in VHDL using the software Xillinix ISE I Need report on circuits diagrams, truth table, and simulations results the structure report should go by 1-introduction 2-block diagram 3-Technical Words 4-Implementations 5-Results 6-Conclusion

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    FFT working in VHDL Завершено left

    I want a VHDL code to achieve a N point FFT

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    Trophy icon Explanation of VHDL code Завершено left

    I have a VHDL code.. I need someone to explain that code in detail to me.. what stuff it is doing on board..

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    Гарантированный
    Project for Ahmed M. -- 6 Завершено left

    Hi Ahmed M., Write VHDL code for frequency comparison on threshold base after the FFT_64 block in my code, the threshold will be defined by user through VIO or uart. The results should be verified on ILA in Hz. Also comment every line of code.

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    Initial Milestone : Write VHDL code for frequency comparison on threshold base after the FFT_64 block in my code, the threshold will be defined by user through VIO or uart. The results should be verif on ILA

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    Project for Ahmed M. Завершено left

    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. I'm a friend of Alessandro that contact you for a mini ...Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. I'm a friend of Alessandro that contact you for a mini project of VHDL

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    Vhdl UART communication code Завершено left

    Hello That I want is a basic uart communication with fifo buffer I have a small code ready At last I want a small call for explain

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    SPI Master Завершено left

    I want SPI master in VHDL for writing and reading from flash IS25WP032

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    NVIDIA GPU Acceleration. Завершено left

    I need to generate a code from C++ to VHDL Using GPU.

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    VHDL FPGA Project Завершено left

    This Project focuses on the use of VHDL language to describe a simple design and to verify its correct operation through test benches and simulations. The implementation on a specific FPGA has to allow also to obtain additional information of consumption, frequency of operation, etc. In short, it is a matter of following a design process as close to

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    Vhdl project Завершено left

    It is a cluster related vhdl project.

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    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

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    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

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    Anyone expert in vhdl Завершено left

    Vhdl is needed

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    $20 / hr Ср. ставка
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    I would like a VHDL code that reads 3 txt file and produces 3 txt file. The inputs text files produced by Matlab in binary. please see the attachment for the code I attempted to do but it not working, and text​ input files.

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    Zen Protocol Miner in Verilog/VHDL Завершено left

    Implement the Zen Protocol in the FPGA and update the Mining App

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    VHDL game using LED and 7-Segment Завершено left

    using VHDL: It’s a simple game of ping pong but only one line using the LED lights. the light will go backward and forward, the player needs to click on control at the edge of last two LED to flip the direction of the LED lights, it will start slow and it will speed up as you play, and the seven segment display will display how many time you hit the

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    Diseño FPGAs en VHDL Завершено left

    Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas...

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    VHDL questions Завершено left

    I have some VHDL questions which I nedd to be solved .

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