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    1,859 vhdl работ(-а,-ы) найдено, цены указаны в USD

    Добрый день всем! Есть алгоритм написанный в матлабе, алгоритм не большой. простой( пара массивов, пара циклов, простейшие вычисления) Необходимо его реализовать в VHDL. Спасибо.

    $23 (Avg Bid)
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    4 ставки
    Circuit Design Engineer 2 дней(-я) left

    We are looking for a talented and driven hands on Electrical Engineer who will be part of creating an incredible cutting edge technology system. And will focus on the design, construction, and troubleshooting of compact and reliable embedded electrical systems . This includes electrical sub-system design, integration, PCB layout, and frequent hands-on work in lab building and debugging electrical ...

    $35 / hr (Avg Bid)
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    I am using Altera DE2-115 FPGA board to configure it using Quartus software 17 lite edition. We have to use QSYS to assign addresses and link the processor, then assign inputs and outputs in VHDL and pin planner in Quartus, and then use NIOS II processor for Eclipse to write a program in C and run the board. I am seeking some help in building this mini thing. I am attaching a pdf file for the tas...

    $22 / hr (Avg Bid)
    $22 / hr Ср. ставка
    14 ставки
    FIR filter Design using FPGA Завершено left

    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

    $112 (Avg Bid)
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    12 ставки

    I am currently using Altera DE2-115 FPGA board to configure it using Quartus 17 lite edition software and write the code in VHDL. We have to use QSYS, and NIOS II for Eclipse to write a program in C and to run the board. I am seeking some help in building this mini thing.

    $27 (Avg Bid)
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    2 ставки
    FPGA DESIGN ENGINEER Завершено left

    We are seeking 1 FPGA Design Engineer for our new product development. FPGA Design Engineer Responsibilities: • Completing implementation in RTL • Ensuring robust and complete timing constraints • Optimizing FPGA code to balance performance, area, power, complexity and timing • Determining and executing development, integration, bring-up and test plans. • Working closely ...

    $37 / hr (Avg Bid)
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    25 ставки
    GL algorithm Expert Завершено left

    hello, I am looking for expert who build GL algorithm using VHDL. If you can do it, we will discuss in details.

    $37 (Avg Bid)
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    7 ставки
    FPGA/VHDL/Verilog Завершено left

    Looking for implementation of a Ethernet Tester, generating and analyzing Ethernet traffic at 1G and 10G. More details on PM. J

    $12 / hr (Avg Bid)
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    25 ставки
    BCD adder VHDL using vivado Завершено left

    BCD adder vhdl code which detects an overflow using vivado

    $8 (Avg Bid)
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    Please read carefully. You need to fix my code. I will sent to you in messages my project. Here is project description: The brightness measurement with help of PMODALS sensor ([войдите, чтобы посмотреть URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([войдите, чтобы посмотреть URL]) is to be used, which takes over the...

    $522 (Avg Bid)
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    GPS implementation Завершено left

    first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PCB of the board you have. U3 is ...

    $336 (Avg Bid)
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    Project for Rajagopal S. Завершено left

    Hi Rajagopal S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. The brightness measurement with help of PMODALS sensor ([войдите, чтобы посмотреть URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([войдите, чтобы посмотреть URL]) is to be used, which takes over the ...

    $220 (Avg Bid)
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    1 ставки
    Develop VHDL code for HX711 Завершено left

    Provide VHDL code and testbench simulation for ECP5 Lattice device (Diamond Studio) to read HX711 sample ([войдите, чтобы посмотреть URL]) And store it in 32bit register

    $177 (Avg Bid)
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    Research help -- 3 Завершено left

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

    $316 (Avg Bid)
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    8 ставки

    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

    $33 / hr (Avg Bid)
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    I need vhdl code for signal processing. I need 256 point fir filter and 4096 point fft. create bid, many experience in signal processing. chatting discussing in detail

    $160 (Avg Bid)
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    Need example code de-10 Завершено left

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

    $110 (Avg Bid)
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    Scope includes the programing (vhdl) for the measurement and of AC voltage, currents, Power (active, reactive and apparent power) and Power Factor in FPGA (Spartan-6). Interfacing ADC and sensors with FPGA for current and voltage measurements. It also includes the display of measured parameter on LED display which is inbuilt on board). This is the brief requirement, interested people may contact ...

    $103 (Avg Bid)
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    Complex Signal Mixer VHDL Завершено left

    Design and Document a VHDL Complex Mixer • Design should contain two 11-bit complex NCOs (Numerically Controlled Oscillator): • Assume clock freq of 100MHz • NCO #1: 11MHz • NCO #2: 18MHz • Design a complex multiplier component • Multiply the outputs of NCO #1 and #2 • Write the outputs of the NCOs and Complex Multiplier to a text file Theory of operation Detai...

    $69 (Avg Bid)
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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only) I don't want imaginary freelancer, please.

    $103 (Avg Bid)
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    15 ставки

    Have several ways to effectively reduce sidelobe the ACAR. In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal. I want to do all the processing with one FPGA without using any other block like DDS. There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for correspon...

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    Project for Jin Q. Завершено left

    Hi Jin :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the val...

    $30 (Avg Bid)
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    1 ставки
    Project for Nick B. Завершено left

    Hi Nick :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the va...

    $30 (Avg Bid)
    $30 Ср. ставка
    1 ставки
    Project for Jin C. Завершено left

    Hi Jin :) I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display..however my code is glitchy...if you could help me fix it it'd be a life...

    $30 (Avg Bid)
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    1 ставки
    Temperature sensor and FPGA Завершено left

    Need to write VHDL program for Genesys 2 board for connecting a temperature sensor to xadc pin and display it in external LCD board

    $62 (Avg Bid)
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    Handson training required on Xilinx Zc-702 including device programming in vhdl and its interfacing with perepherels like ADC, DAC, Memory etc.

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    FPGA and Vhdl expert needed Завершено left

    I have problem in "fpga" I can't how to interface between power stage card and "fpga" card Can you write program in "vhdl" language?

    $20 (Avg Bid)
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    Wanted Online FPGA Tutor Завершено left

    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

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    FPGA Development Завершено left

    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

    $906 (Avg Bid)
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    Hi, We are looking for an experienced electronics engineer and software engineer, The project is to design a smart Home Cinema controller, the aim is to send data to a database, reading and writing data of different Video Projectors, Amplifiers, and many more devices via HDMI, USB, RS232, Ethernet, IR and many more. You will conceptualise the electronics and software for the system. We are stric...

    $56 / hr (Avg Bid)
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    18 ставки
    Filtro de 3 bandas en vhdl Завершено left

    Implemente un sistema de ecualización en tiempo real de tres bandas (bajos, medios y altos) en el FPGA de xilixn. Desarrolle los tres filtros necesarios para el ecualizador, los puede establecer en matlab o labview. Una vez definidos los coeficientes del filtro impleméntelos en el FPGA (a través de Matlab, Laview o Multisim). Se establece un bonus de 4 puntos para el grupo qu...

    $183 (Avg Bid)
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    5 ставки
    Counter in VHDL Завершено left

    Create a design with two counters and a 7-Segment Display • The first “Fast Counter” should count up 0 -> 49999999 and then reset to zero • When the Fast Counter reaches 49999999 it should output a single pulse on the “o_max_val” output to the second counter • The second counter (4-bit) counter should include a “i_count_enable” input, connected...

    $30 (Avg Bid)
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    1 ставки

    I need a simple VHDL program for measuring the time between two input signals. The VHDL program should be in structural code and should includes modules like Counter, BCDtoASCI, UART and FStateMachine + top level. I need also for every module and for the hole program testbenches.

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    Hey, I have working project in simulation that when I try to run it on board it doesn't work. I need someone with that board or that have familiar board to notice if there is problem with my code.

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    This includes the development of vhdl code for PWM generator, PID controller, flux estimator etc. Training would be web based on Skype or webex.

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    4-bit vhdl divider Завершено left

    It is required to design a 4-bit binary divider. The division can be limited to un-signed numbers only. Feel free to implement the divider by any architecture you like, but be sure to understand and be able to verify the operation of the selected architecture. Fig. 1 shows a binary division example to recap the binary division process. -Structural and behavioral codes for the binary divider using...

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    Add uart to MIPS Завершено left

    I Have mips in VHDL code, I want to add to it UART

    $35 (Avg Bid)
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    help running mips on FPGA Завершено left

    I got MIPS in VHDL, but when I run it on FPGA, It seems to do nothing, although it's working in simulation.

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    Dice game in VHDL for board Завершено left

    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [войдите, чтобы посмотреть URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 t...

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    Wristwatch-VHDL -- Vivado Завершено left

    Design a multifunction wristwatch that has time-keeping, alarm, and stopwatch functions. The wristwatch has three buttons (B1, B2, and B3) that are used to change the mode, set the time, set the alarm, start and stop the stopwatch, and so on. Pushing button B1 changes the mode from Time to Alarm to Stopwatch and back to Time. The functions of other buttons vary depending on the mode.

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    Design principle (VHDL) Завершено left

    RTL design project All of the data required to explain what I want are found in the attached file

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    Dice game VHDL Завершено left

    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [войдите, чтобы посмотреть URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 t...

    $8 (Avg Bid)
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    1 ставки
    VHDL project Завершено left

    Anyone who is good in VHDL and can help me in implementing load, move, add, xor

    $2 / hr (Avg Bid)
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    1 ставки

    Design a circuit that emulates an alarm system, which is armed and disarmed with a code consisting of 4 symbols given by the buttons on the board (for example btnC, btnL, btnR, btnU). The alarm is armed or disarmed when the correct code combination is entered. When the alarm is disarmed, LED0 is on, when the alarm is armed, LED15 is on. SW0 is a sensor, when the alarm is armed and SW0 = 1, the LED...

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    VHDL project Завершено left

    I need a vhdl project that integrates IoT and communications.

    $212 (Avg Bid)
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    3 ставки
    DICE GAME in VhDL Завершено left

    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [войдите, чтобы посмотреть URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 t...

    $78 (Avg Bid)
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    6 ставки

    I need single cycle 32 bit mips vhdl coding to find prime numbers. I will provide code to find prime number so you just have to build cpu for this specific purpose and I am also going to provide parameters for this architecture. I am gonna share project file after finalising with best person to do this job

    $157 (Avg Bid)
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    3 ставки