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    5,489 vlsi verilog fpga asic работ(-а,-ы) найдено, цены указаны в USD
    New ASIC SH Завершено left

    Здравствуйте, Ankita L.! Я обратил внимание на ваш профиль и хотел бы предложить вам свой проект. Мы можем обсудить детали в чате.

    $10 (Avg Bid)
    $10 Ср. заявка
    1 заявок(-ки)
    Project for Pavlo H. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)
    Project for Mykyta M. Завершено left

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Ср. заявка
    1 заявок(-ки)
    $111 Ср. заявка
    1 заявок(-ки)

    Разработка системы Формирования звуковых оповещений на основе FPGA,(Development of a system for generating sound notifications based on FPGA.)

    $38 (Avg Bid)
    $38 Ср. заявка
    3 заявок(-ки)
    Project for Sergey G. Завершено left

    Здравствуйте, Sergey G.! Я обратил внимание на ваш профиль и хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $35 (Avg Bid)
    $35 Ср. заявка
    1 заявок(-ки)
    Project for Oleksandr S. Завершено left

    Здравствуйте, Clevermindolex! Хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

    $30 - $30
    $30 - $30
    0 заявок(-ки)

    Цветомузыка. Адресная светодиодная лента, фильтр по частотам (высокие, средние, низкие), в зависимости от громкости и частоты мигает лента разными цветами

    $17 (Avg Bid)
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    1 заявок(-ки)

    ! Нужно сделать SEO оптимизацию для интернет магазина где продаются Асики для майнинга. -- Информация о сайте WebSite: [войдите, чтобы посмотреть URL] Сайт создан на конструкторе satu.kz. Title Asic Mining в Казахстане – Купить asic для майнинга. Keywords asic, asic miner, купить асик, купить асик в казахстане, asic цена, asic miner купить, купить асик в астане, асик, майнинг, mine...

    $90 (Avg Bid)
    $90 Ср. заявка
    19 заявок(-ки)

    Linux Другое или затрудняюсь ответить Конфигурация прошивки на asic Майнер s9. Перезборка ядра, отключение ограничения на скорость вращения вентиляторов, полное их отключение. Создание прошивки для первичного запуска.

    $155 (Avg Bid)
    $155 Ср. заявка
    1 заявок(-ки)

    Implementation of Adaptive Filter for echo cancellation using FPGA and verilog.

    $27 / hr (Avg Bid)
    $27 / hr Ср. заявка
    2 заявок(-ки)
    Prospect for mining proposal 6 дней(-я) left
    ПОДТВЕРЖДЕН

    I need a PDF sheet where the best mining products will be presented. With informations of possible ROI [войдите, чтобы посмотреть URL] there can be taken informations Name will be Folex-mining, Logo I will send you. Also the sheet should look professional and the informations should be there written fully. 4-5 asic miner should be there. And 2 sections of time contracts. Where I will write...

    $40 (Avg Bid)
    $40 Ср. заявка
    16 заявок(-ки)
    Project for Miguel B. 8 дней(-я) left

    Hi Miguel B., I noticed your profile and would like to offer you my project. We can discuss any details over chat. I have hired you before with different Verilog Projects and really like how fast and helpful you are. Please let me know if you are able to do my project. Also we can change the budget. Thank you!

    $30 (Avg Bid)
    $30 Ср. заявка
    1 заявок(-ки)

    Hello, i need to compile custom firmware for most important S9, S9i, L3+ if it possible also for X3, E3, B3. Need to compile with custom fee with custom address, 1% 3% 5% fee. We do monitoring and hosting for ASICS so my customers will pay with fee.

    $540 (Avg Bid)
    $540 Ср. заявка
    10 заявок(-ки)
    snake leader game 5 дней(-я) left

    use verilog language to make snake and leader game

    $31 (Avg Bid)
    $31 Ср. заявка
    6 заявок(-ки)
    Fpga designing -- 2 4 дней(-я) left

    Hi I need help for my project on FPGA board for implementation of design using Vhdl. Please contact asap.

    $26 (Avg Bid)
    $26 Ср. заявка
    13 заявок(-ки)
    PCIe on Xilinx FPGA 4 дней(-я) left
    ПОДТВЕРЖДЕН

    Need to develop a system that uses PL based logic to implement PCIe bus for communication with PC

    $501 (Avg Bid)
    $501 Ср. заявка
    1 заявок(-ки)

    I just need help with this Verilog assignment asap

    $35 (Avg Bid)
    $35 Ср. заявка
    23 заявок(-ки)

    i need to convert RGB RAW (i guess its RGB888) to DVI (not hdmi to avoid licensing cost). the paymentis for the design/knowledge, meaning all design files+software will be delivered and explained. I prefer using "of the shelf" video IC's, and not DSP/FPGA implementation. need someone experienced & familiar with video formats converter. Thanks in advance Doron

    $658 (Avg Bid)
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    6 заявок(-ки)

    a very simple verilog project call me for the details

    $179 (Avg Bid)
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    14 заявок(-ки)
    verilog code 1 день left

    Looking for some help with my verilog code project .. please help if you can ..

    $13 - $20
    Скрытый
    $13 - $20
    8 заявок(-ки)
    Simulating LC-3 Machine on SystemVerilog Заканчивающийся left
    ПОДТВЕРЖДЕН

    LC-3 simulation not functioning, all inputs on to a FPGA board is returning 0s. Finished with 90% of the code, needs help with running and debugging

    $50 (Avg Bid)
    $50 Ср. заявка
    4 заявок(-ки)
    I need expert in VLSI Завершено left

    VLSI design and electerical engineering

    $23 (Avg Bid)
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    5 заявок(-ки)

    Build and config cluster network on my PC (windows 10) that use my CPU resource from asic (antminer s9) on network. For use cgminer Asic machine: antminer s9 Req: exp doing that before!!! ***BID above budget will be delete automatic.*** for more details leave msg. ***NO MILESTONE FOR START*** ****FULL PAYMENT WHEN JOB DONE****

    $104 (Avg Bid)
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    1 заявок(-ки)

    CHANGE ALGORITHM FROM SHA-256 TO Scrypt or EtHash ON ASIC Antminer Asic machine: antminer s9 this asic work on sha-256 algorithm and it need to be change to Scrypt or EtHash algorithm. Req: exp before doing that exp with karnel exp with ssh ***BID above budget will be delete automatic.*** for more details leave msg. open source: [войдите, чтобы посмотреть URL] [войдите, чтобы посмотреть ...

    $75 (Avg Bid)
    $75 Ср. заявка
    1 заявок(-ки)

    Build and config cluster network on my PC (windows 10) that use my CPU resource from asic (antminer s9) on network. For use cgminer Asic machine: antminer s9 Req: exp doing that before!!! ***BID above budget will be delete automatic.*** for more details leave msg. ***NO MILESTONE FOR START*** ****FULL PAYMENT WHEN JOB DONE****

    $60 - $75
    $60 - $75
    0 заявок(-ки)

    modelsim is must Add-Sub unit with Register file (3-ported RAM) 3-ported register file, 32 bit registers, add/sub unit.

    $25 (Avg Bid)
    $25 Ср. заявка
    4 заявок(-ки)

    n bit adder. waveform in modelsim for N=32 mif file, This is an integration Take Adder/Subtractor Memory Block Labs LPM 3 PORT RAM FOR N=32 bits

    $24 (Avg Bid)
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    4 заявок(-ки)
    A VLSI task using C++ Programming Завершено left

    A VLSI task using C++ Programming needs to be completed in next 24 hours

    $23 (Avg Bid)
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    3 заявок(-ки)
    Simple Processor VHDL Code Завершено left

    Complete the skeleton code of this simple processor. Language must be VHDL and not Verilog. The attached file provides an outline of what must be completed.

    $36 (Avg Bid)
    $36 Ср. заявка
    10 заявок(-ки)

    I am hiring electrical engineers having good experience in following microcontrollers 1) Arduino 2) Raspberry Pi 3) PIC microcontroller 4) FPGA 5) Cortex M4/M7 Mention you areas of expertise in your bid. I would encourage new freelancers to apply.

    $22 - $187
    Скрытый
    $22 - $187
    17 заявок(-ки)
    ether bit stream for fpga vcu1525 Завершено left

    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat..

    $1800 (Avg Bid)
    $1800 Ср. заявка
    1 заявок(-ки)

    Hi Giles B., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $1800 (Avg Bid)
    $1800 Ср. заявка
    1 заявок(-ки)
    $26 Ср. заявка
    3 заявок(-ки)
    ReconOS expert(ONLY!!!!) needed Завершено left

    Dear reader, If you are an FPGA SoC expert with at least five years of experience in C, scripting, kernel programming, RTOS, FPGA, SOC, and Softcore processors, please kindly contact me. Best regards

    $665 (Avg Bid)
    $665 Ср. заявка
    7 заявок(-ки)
    image processing -- 5 Завершено left

    I want Architecture of sobel edge detection and its implementation on fpga

    $112 (Avg Bid)
    $112 Ср. заявка
    4 заявок(-ки)
    image processing -- 4 Завершено left

    I am doing project on sobel edge detection on images which will be implemented in FPGA so i need architecture for sobel edge detection which will detect the edge of the image in fpga.

    $16 (Avg Bid)
    $16 Ср. заявка
    1 заявок(-ки)
    CRC-7 FPGA Verilog Implementation Завершено left

    Implement CRC-7 checker module using Verilog HDL (no IP cores) and the test bench, that provides sufficient testing for the module. Consider naming the module signals as clk, rst, check (for input enable), data_in (for message + CRC), out (message check result). If you know how to develop a CRC module capable of 1 bit error correction, then tell me your considerations and probably we can change ...

    $28 (Avg Bid)
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    6 заявок(-ки)
    Project for Shweta P. Завершено left

    Hi Shweta, I saw your profile and maybe we can work to a project together. we have multiple FPGA units(especially blackminer F1 ultra).We would like someone to test a Kawpow bitstream on the unit. the F1ultra is using 6x of Xilinx Kintex-7 420T chips. what is a possible theoretical hashing power expressable? contact me if interested, we can find multiple middle ways and agreements if interested...

    $581 (Avg Bid)
    $581 Ср. заявка
    1 заявок(-ки)
    ether bit stream for fpga Завершено left

    i have fpga vcu1525 card, so i want ether bit stream, is urgent and very serious project, so If anyone can make this project let them contact.

    $1050 (Avg Bid)
    $1050 Ср. заявка
    2 заявок(-ки)
    Vivado model Завершено left

    (Don't make bid before you read) I developed a verilog code for data recovery using some techniques and I want to analyse the output in Vivado and measure the noise and see how the system can cope with it

    $41 / hr (Avg Bid)
    $41 / hr Ср. заявка
    4 заявок(-ки)

    Build and config cluster network on my PC(windows 10) that use my CPU resource from asic (antminer s9) on network. For use cgminer Asic machine: antminer s9 Req: exp doing that before!!! for more details leave msg.

    $65 (Avg Bid)
    $65 Ср. заявка
    3 заявок(-ки)
    vhdl & fpga programing Завершено left

    tutor for my classes in vhdl programming and fpga programming for university

    $23 / hr (Avg Bid)
    $23 / hr Ср. заявка
    13 заявок(-ки)

    Project: Microcontroller Communication over Ethernet Subject: Data transfer between two zybo boards which are connected to laptop. Software: Vivado 2018.3 Hardware: Zybo board (Not mandatory to have it with you, testing part will be done at our end) Eg: If we try to send character "a" from one zybo board to another, it has to pick up and turn on the LED.

    $334 (Avg Bid)
    $334 Ср. заявка
    7 заявок(-ки)

    Project: Microcontroller Communication over Ethernet Subject: Data transfer between two zybo boards which are connected to laptop. Software: Vivado 2018.3 Hardware: Zybo board (Not mandatory to have it with you, testing part will be done at our end) Eg: If we try to send character "a" from one zybo board to another, it has to pick up and turn on the LED.

    $455 (Avg Bid)
    $455 Ср. заявка
    2 заявок(-ки)
    Looking For FPGA Expert Завершено left

    This project is work on one video conference project using FPGA Board. Further details will be shared later ... Interested candidate feel free to chat

    $407 (Avg Bid)
    $407 Ср. заявка
    8 заявок(-ки)

    1. Complete the modelling of design solution in Verilog HDL. 2. Obtain a bug-free compiled HDL code of the design solution. 3. Write the Verilog testbench to simulate the obtained design. 4. Conduct unit testing and integration testing of the design. 5. Evaluate the deep pipeline using test codes and the Active HDL simulator. maybe this code will help you ( it's a code for 5-stages ) [в...

    $178 (Avg Bid)
    $178 Ср. заявка
    12 заявок(-ки)