Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Нанять Verilog / VHDL Designers

Фильтр

Мои последние поисковые запросы
Фильтровать по:
Бюджет
по
по
по
Тип
Навыки
Языки
    Статус работы
    17 работ(-а,-ы) найдено, цены указаны в USD
    VHDL FPGA counter 00-99 6 дней(-я) left
    ПОДТВЕРЖДЕН

    I need a counter 00-99 at 2 digits of seven segment display with frequency 1hz p.m. for more info

    $30 (Avg Bid)
    $30 Ср. заявка
    5 заявок(-ки)
    Helping in desiging a digital Delay locked loop 5 дней(-я) left
    ПОДТВЕРЖДЕН

    I have a verilog model for DLL and the model needs to modify it based on some requirements. This is simple task for the one who has a good background in this context but you will get benifit from continuing with me in this project

    $25 (Avg Bid)
    $25 Ср. заявка
    2 заявок(-ки)
    Project of Programming a micro controller 5 дней(-я) left
    ПОДТВЕРЖДЕН

    i have a project in 2 step.. first is to implementation of microcontroller in C and later to complete project 2

    $184 (Avg Bid)
    $184 Ср. заявка
    23 заявок(-ки)
    Networking Simulation Project Expert 5 дней(-я) left
    ПОДТВЕРЖДЕН

    - Comparing and analysis the performance of existing protocols such as Epidemic, Spray and Wait and PROPHET using ONE Simulator - Required to design and create new routing protocol based on existing protocols such as Epidemic, Spray and Wait and PROPHET protocols using ONE Simulator. - Implement and simulate the new routing protocol using ONE Simulator

    $195 (Avg Bid)
    $195 Ср. заявка
    2 заявок(-ки)
    Vitis AI Coach 5 дней(-я) left
    ПОДТВЕРЖДЕН

    Searching for someone with experience in Vitis AI and various HLS optimization techniques. Please leave your hourly rate and experience with Vitis AI. Memory access and computation optimization.

    $32 / hr (Avg Bid)
    $32 / hr Ср. заявка
    9 заявок(-ки)
    build FPGA to mine bitcoin or other type of crypto currencies 4 дней(-я) left
    ПОДТВЕРЖДЕН

    Anyone interest in building FPGA to mine bitcoin or other type of crypto currencies.

    $546 (Avg Bid)
    $546 Ср. заявка
    5 заявок(-ки)
    Modify LimeSDR FPGA 4 дней(-я) left

    The LimeSDR-USB allows to either transmit signals at once or schedule them. In all cases the samples must be passed from the host to the device at each call, which can take time due to the USB speed and latency. We would like to be able to just tell the device to transmit a specific type of signal, either at once or at a specific timestamp, without passing the samples each time. The different sig...

    $2675 (Avg Bid)
    $2675 Ср. заявка
    8 заявок(-ки)
    Program a microprocessor 3 дней(-я) left

    I have a circuit which needs to communicate to an external microprocessor.

    $40 (Avg Bid)
    $40 Ср. заявка
    6 заявок(-ки)
    who knows verilog hdml, quartus and modelsim. 3 дней(-я) left
    ПОДТВЕРЖДЕН

    I need someone who knows verilog hdml, quartus and modelsim.

    $15 (Avg Bid)
    $15 Ср. заявка
    2 заявок(-ки)
    power system experts required 2 дней(-я) left
    ПОДТВЕРЖДЕН

    deadline: 8 hours project is about optimal power flow using barnacles mating optimizer with applied matpower in case IEEE 30 bus.., I want you fix my opf coding to get the result fuel cost and power loss.., and the relate my algorithm to matpower toolbox.., for matpower, i use case_ieee30, that's all, and also in the result i want keep power output for generator, bus voltage, shunt capacito...

    $120 (Avg Bid)
    $120 Ср. заявка
    2 заявок(-ки)
    Multicycle project -- 2 2 дней(-я) left
    ПОДТВЕРЖДЕН

    Multicycle project xilinix vhdl

    $35 (Avg Bid)
    $35 Ср. заявка
    4 заявок(-ки)

    Write 16 bit RISC processor verilog code and test bench code in structural programming. Explain the working of the code. Write a report of the project too. Don't write code in behavioral programming. Preferred software (ISE PROJECT NAVIGATOR)

    $75 (Avg Bid)
    $75 Ср. заявка
    3 заявок(-ки)
    ASIC IP RTL/TB Development - Looking for Engineers -- 3 2 дней(-я) left
    ПОДТВЕРЖДЕН

    Job Description :- We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs. The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic, Clock-gating ...

    $561 (Avg Bid)
    $561 Ср. заявка
    9 заявок(-ки)
    MPI Programming , Parallel programming ,MPI graphs 1 день left
    ПОДТВЕРЖДЕН

    Hello I would like help with MPI graphs MPI Programming , Parallel Programming , Protocol Tarry, Protocol Echo

    $102 (Avg Bid)
    $102 Ср. заявка
    2 заявок(-ки)
    Compiler Design 1 день left

    I need to compile a programming language to output quadruples for variable declaration and assignment statement using c plus plus

    $22 (Avg Bid)
    $22 Ср. заявка
    5 заявок(-ки)
    Microprocessor systems help 20 часов(-а) left

    you are required to create your own device. You are allowed to chose your own topic, however, it should meet the minimum requirements listed below. There will be points distributed for creativity, keep that in mind. Your setup should feature microcontroller to microcontroller communication. Additionally you must use at least 3 of the following systems: Matrix based input Matrix based output Tim...

    $40 (Avg Bid)
    $40 Ср. заявка
    4 заявок(-ки)

    Parsing Infix notation to ONP i Verilog [FGPA] and calculating the value in two modules

    $30 (Avg Bid)
    $30 Ср. заявка
    2 заявок(-ки)