Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Нанять Verilog / VHDL Designers

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    22 работ(-а,-ы) найдено, цены указаны в USD
    Circuit design 6 дней(-я) left

    Need a circuit integrating multiple simple circuits

    $350 (Avg Bid)
    $350 Ср. заявка
    11 заявок(-ки)

    The project is to design a system with an FIR filter for voice filtering in real-time. The work will be on Xilinx and Modelsim to design the system and also with Matlab so it's a big project and require time. It's a big project but the budget is average so please don't bid me high.

    $557 (Avg Bid)
    $557 Ср. заявка
    7 заявок(-ки)

    The project is to design a system with an FIR filter for voice filtering in real-time. The work will be on Xilinx and Modelsim to design the system and also with Matlab so it's a big project and require time. It's a big project but the budget is average so please don't bid me high.

    $210 (Avg Bid)
    $210 Ср. заявка
    3 заявок(-ки)
    Basic calculator using vivado on basys3 fpga 5 дней(-я) left
    ПОДТВЕРЖДЕН

    To whom it may concern, I'm looking for someone experienced who can develop a basic calculator using verilog on vivado with specific requirements in a short period of time. If you think this fits your skills, let me know and lets discuss things further!

    $23 (Avg Bid)
    $23 Ср. заявка
    6 заявок(-ки)
    Verilog on a weekend :) 5 дней(-я) left
    ПОДТВЕРЖДЕН

    Hi, I have a couple of Verilog questions and would be happy to pay to pick someones brain! Attached is a simple HLS program that I synthesized to Verilog. I have some experience writing very basic Verilog programs, but some of the stuff would need an explanation. Attached is the Verilog project. And below in the text you will find the original HLS snippet. Ideally we would walk through the code an load the Verilog into Vivado and play a bit around with it for 2-3 hours while I ask a couple of questions. (1) CORDIC method is it applied here? (2) How does the entire program work? Honest question. (3) Why is there so much paramter overhead etc? (4) How would you simplify the application in Verilog? Requirements === (1) Happy to grab a Zoom or phone call (asked support seems to be okay) (2...

    $44 / hr (Avg Bid)
    $44 / hr Ср. заявка
    5 заявок(-ки)

    I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite)

    $37 (Avg Bid)
    $37 Ср. заявка
    2 заявок(-ки)
    Need someone good expert in computer architecture -- 2 4 дней(-я) left
    ПОДТВЕРЖДЕН

    you will be implementing a pipelined MIPS processor datapath with the following features: 1) FDEMW 5-stage pipeline with branch

    $15 (Avg Bid)
    $15 Ср. заявка
    3 заявок(-ки)
    Verilog programming-2 4 дней(-я) left
    ПОДТВЕРЖДЕН

    Verilog programming project using Vivado. please bid if you can assist

    $40 - $53
    Скрытый
    $40 - $53
    6 заявок(-ки)
    FPGA Project 4 дней(-я) left

    1 Verilog/VHDL Programming language 2 Understanding of the protocol and standards 3 FPGA knowledge & Programming hands on 4 Knowledge of the safety standards. Optical Data link 5 Networking concepts

    $379 (Avg Bid)
    $379 Ср. заявка
    9 заявок(-ки)
    VERILOG code 4 дней(-я) left

    i need people who are very proficient in verilog, i will be giving few tricky question they need to help me

    $19 (Avg Bid)
    $19 Ср. заявка
    2 заявок(-ки)
    Adder Architecture 4 дней(-я) left

    Need help designing an adder architecture in Verilog/Systemverilog.

    $20 (Avg Bid)
    $20 Ср. заявка
    6 заявок(-ки)
    Need someone good expert in computer architecture 3 дней(-я) left
    ПОДТВЕРЖДЕН

    you will be implementing a pipelined MIPS processor datapath with the following features: 1) FDEMW 5-stage pipeline with branch

    $20 (Avg Bid)
    $20 Ср. заявка
    1 заявок(-ки)
    Image Equalizer 3 дней(-я) left

    I need an image equalizer written in VHDL language. The semplified algorithm to use should be: DELTA_VALUE = MAX_PIXEL_VALUE – MIN_PIXEL_VALUE SHIFT_LEVEL = (8 – FLOOR(LOG2(DELTA_VALUE +1))) TEMP_PIXEL = (CURRENT_PIXEL_VALUE - MIN_PIXEL_VALUE) << SHIFT_LEVEL NEW_PIXEL_VALUE = MIN( 255 , TEMP_PIXEL) In this project the program recieve the image dimension in 2 bytes, the first one is for columns and the second one is for rows. The third byte is the first byte of the image that the program recieves in input. Extra Notes: 1. FLOOR(LOG2(DELTA_VALUE +1)) is an integer number 2. The project should be able to process more than one image, but the input image will never change during the execution, only when the DONE signal is high 3. The module will start processing when the S...

    $205 (Avg Bid)
    $205 Ср. заявка
    7 заявок(-ки)

    I am using a 32x32 LED matrix from Adafruit and I am driving it with an FPGA. I followed the tutorial they provided and I get an image initialize. Now, I am trying to have various frames to show, to make some sort of video. I want to use a microcontroller to send the data for the frames to the FPGA. Further explanation is attached on the word document and all the files I currently am using will also be attached. Please don't hesitate to reach out with any questions regarding the design.

    $668 (Avg Bid)
    $668 Ср. заявка
    15 заявок(-ки)

    For more details, contact me via chat

    $194 (Avg Bid)
    $194 Ср. заявка
    10 заявок(-ки)
    Ac voltage measurement circuit 2 дней(-я) left
    ПОДТВЕРЖДЕН

    ac voltage measurement circuit and output of this circuit is in adc and send to pic16f877a

    $20 (Avg Bid)
    $20 Ср. заявка
    10 заявок(-ки)
    Design 4 bits arithmetic unit that add, multiply and subtract 2 дней(-я) left
    ПОДТВЕРЖДЕН

    Design 4 bits arithmetic unit that add, multiply and subtract using PTL & Domino *****simulate using cadence***** The app takes 3 inputs A, B, and C A, and B are 4 bits operands C is a 2 bits number (input for a multiplexing circuit) representing the operation Deliverables: 1- a step by step word file of the work done 2- all cadence files

    $33 (Avg Bid)
    $33 Ср. заявка
    3 заявок(-ки)
    Verilog programming 1 день left
    ПОДТВЕРЖДЕН

    Verilog programming project using Vivado. please bid if you can assist

    $20 - $33
    Скрытый
    $20 - $33
    5 заявок(-ки)
    Small VHDL project starting from a project 1 день left
    ПОДТВЕРЖДЕН

    I need someone who can develop a current small project written in VHDL. It should be a game dispaying on vga monitor.

    $73 (Avg Bid)
    $73 Ср. заявка
    6 заявок(-ки)
    I need VHDL/Quartus Expert from Pakistan 1 день left
    ПОДТВЕРЖДЕН

    To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), memory system, control unit etc. separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the FPGA board

    $11 - $18 / hr
    Скрытый
    $11 - $18 / hr
    1 заявок(-ки)
    VHDL/Quartus Expert from Pakistan.... 1 день left
    ПОДТВЕРЖДЕН

    To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), memory system, control unit etc. separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the FPGA board

    $22 - $181
    Скрытый
    $22 - $181
    2 заявок(-ки)
    Looking for someone to write a scope for my project 15 часов(-а) left
    ПОДТВЕРЖДЕН

    Title of the project HDL Digital Signal Processor core for FPGA implementation Deadline is in 15 hours budget is 20$ requirement for the scope will be through the chat Thanks

    $32 (Avg Bid)
    $32 Ср. заявка
    6 заявок(-ки)