Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Нанять Verilog / VHDL Designers

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    17 работ(-а,-ы) найдено, цены указаны в USD

    I have 1.25 Mbps data on an avalon-ST interface to be transferred to the HPS then to the ethernet port on DE1-SOC board. The data are on 24 channels of 24bit samples. I need you to explain the work to me in case I need to modify it or change the platform. My project which collects the data is attached. The top-level file is i2s_dsp

    $41 / hr (Avg Bid)
    $41 / hr Ср. ставка
    2 ставки
    wireless sensor node protocol 6 дней(-я) left

    My project require someone knowledgable in the area of wsn. The main Idea would be enhancing a currently existing routing protocol in wireless sensor nodes, the code can be done in any language, I prefer Matlab and or c++ using omnet++ simulator

    $445 (Avg Bid)
    $445 Ср. ставка
    7 ставки
    FPGA simple circuit board design 6 дней(-я) left
    ПОДТВЕРЖДЕН

    Circuit board designer required for FPGA board with the following specifications. PCI-Express Xilinx Kintex 7 FPGA 50a VCCINT power to FPGA JTAG port (Possible option of 2 x DDR3 SODIMM RAM Slots)

    $1855 (Avg Bid)
    $1855 Ср. ставка
    13 ставки

    I want to do image processing for some of my images its basically a red color segmentation from the image and detect the patterns using verilog..... the image size is 240x240

    $279 (Avg Bid)
    $279 Ср. ставка
    7 ставки
    Program plc 6 дней(-я) left

    get input from banner hi speed sensor and provide output to air cylinder

    $199 (Avg Bid)
    $199 Ср. ставка
    10 ставки

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    $162 (Avg Bid)
    $162 Ср. ставка
    10 ставки
    NEXYS 4 DDR - DSP ( citire semnale si prelucrare ) 5 дней(-я) left
    ПОДТВЕРЖДЕН

    Cu ajutorul placii de dezvoltare Nexys 4 DDR dorim citirea datelor receptionate de o placa ce contine o fotodioda. Semnalele primite sa le afisam si sa le prelucram ulterior cu ajutorul unor algoritmi de filtrare pentru a obtine la final niste date valide.

    $170 (Avg Bid)
    $170 Ср. ставка
    1 ставки

    I am currently working on some small project need to implement an image processing on FPGA, which may include patterns detection after red color segmentation and recognizing the detected patterns....the image size is 240x240 which has some patterns covered in red color

    $106 (Avg Bid)
    $106 Ср. ставка
    5 ставки

    This project need to implement the several LVDS interface between Xinix Atix and a sensor buffer This project is completed after simulating transfer (Buffer content ==> FPGA RAM content) This is the testing project, so that, you can get more projects after completing this. If you have experiences, you can complete within a few days. Deliverables: Verilog & buffer frame communication si...

    $377 (Avg Bid)
    $377 Ср. ставка
    5 ставки
    generate verilig code for quartus ii program 3 дней(-я) left
    ПОДТВЕРЖДЕН

    I have a de1-soc fpga board ([войдите, чтобы посмотреть URL]) for the detail. currently i have difficulty id generating code for image processing for my image. I have a completed matlab code that include the image and filtering kernel. I need the code to run into my fpga board.

    $87 (Avg Bid)
    $87 Ср. ставка
    3 ставки
    Vhdl Mips pipelined project 2 дней(-я) left

    Need a vhdl project on mips pipelined processor

    $152 (Avg Bid)
    $152 Ср. ставка
    8 ставки
    Max10 FPGA <> FT60x <> PC using USB3 and VHDL 1 день left
    ПОДТВЕРЖДЕН

    We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.

    $40 / hr (Avg Bid)
    $40 / hr Ср. ставка
    8 ставки

    Preciso de um profissional com experiência em programação para máquinas POS (point of sale) para criar um sistema de emissão de ingressos. Necessário sistema web para gerenciar as vendas. Possibilidade de pagamento na POS via cartão de crédito/débito. Aguardo interessados para combinar.

    $957 (Avg Bid)
    $957 Ср. ставка
    5 ставки
    Verilog Design 1 день left

    I have one architecture, needs the RTL verilog code for the design to be made and followed by placement and routing to derive the power.

    $138 (Avg Bid)
    $138 Ср. ставка
    10 ставки
    Vivado HLS fixed point code optimization 1 день left
    ПОДТВЕРЖДЕН

    1. Vivado HLS fixed code optimization 2. Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HLS 5. Intergration of IP generated in HLS in Verilog code

    $181 (Avg Bid)
    $181 Ср. ставка
    1 ставки

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design

    $104 (Avg Bid)
    $104 Ср. ставка
    7 ставки

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    $152 (Avg Bid)
    $152 Ср. ставка
    8 ставки