Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Нанять Verilog / VHDL Designers

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    18 работ(-а,-ы) найдено, цены указаны в USD
    ALU design in VHDL 6 дней(-я) left
    ПОДТВЕРЖДЕН

    mini arithmetic logic unit for signed and unsigned numbers

    $18 (Avg Bid)
    $18 Ср. ставка
    5 ставки
    Physical Design Engineer-Soc 6 дней(-я) left

    Looking for a Senior Physical Design Engineer in California only

    $35000 (Avg Bid)
    $35000 Ср. ставка
    1 ставки
    Need Xilinx developer_8263 -- 2 6 дней(-я) left
    ПОДТВЕРЖДЕН

    DESIGN OF NAND MEMORY CONTROLLER ARCHITECTURE FOR BIG DATA STORAGE

    $30 - $250
    $30 - $250
    0 ставки

    I am looking for an engineer who has good knowledge of Codesys for Programmable Logic Controllers (PLC). The freelancer must have experience of doing technical writing as well. More details will be shared with the shortlisted freelancer.

    $176 (Avg Bid)
    $176 Ср. ставка
    3 ставки
    VHDL Verilog 5 дней(-я) left
    ПОДТВЕРЖДЕН

    Kann mir jemand helfen dieses Verilog Problem zu lösen?

    $38 (Avg Bid)
    $38 Ср. ставка
    2 ставки
    Programmable Logic Controllers (PLC) using CODESYS 4 дней(-я) left
    ПОДТВЕРЖДЕН

    Hello Everyone I am looking for an Engineer with sound knowledge of CODESYS for completion of project. More details will be shared with experienced and interested freelancers. The person must have sound knowledge of technical writing as well to handle the description part of the project. Kindly place your competitive bids for further discussion.

    $92 (Avg Bid)
    $92 Ср. ставка
    9 ставки

    Project Description: 2-Stage Project with 2 milestone payments. 1. The 1st stage is completion of the board design (must use Orcad/Cadence software), which includes schematic, printed circuit board and Bills Of Materials. 1st milestone payment on successful completion of 1st stage 2. The 2nd stage is coding the software with good documentation and 2nd milestone payment is made on successful c...

    $596 (Avg Bid)
    $596 Ср. ставка
    44 ставки

    I need parse Verilog (vhdl) code for fpga, structure the same code and rewrite to another fpga. The project is ready.

    $3823 (Avg Bid)
    $3823 Ср. ставка
    17 ставки
    ADC in FPGA 2 дней(-я) left
    ПОДТВЕРЖДЕН

    Implementation of suitable RC filter for ADC. Digital part implementation is done on FPGA. RC filter has to be designed for given specification.

    $22 (Avg Bid)
    $22 Ср. ставка
    8 ставки

    VHDL code of optimization algorithm fixing.

    $59 (Avg Bid)
    $59 Ср. ставка
    9 ставки
    implement a pipelined MIPS proccessor simulator in C++ -- 2 2 дней(-я) left
    ПОДТВЕРЖДЕН

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $167 (Avg Bid)
    $167 Ср. ставка
    3 ставки

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $27 (Avg Bid)
    $27 Ср. ставка
    2 ставки
    1 hour design antenna by CST program 1 день left
    ПОДТВЕРЖДЕН

    i want to design step by step antenna by CST program (spiral antenna) by TeamViewer you will describe to me how to design it

    $120 (Avg Bid)
    $120 Ср. ставка
    13 ставки
    implement a pipelined MIPS proccessor simulator in C++ 1 день left
    ПОДТВЕРЖДЕН

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $169 (Avg Bid)
    $169 Ср. ставка
    3 ставки

    Hello Please check it carefully. /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ......................................................... [войдите, чтобы посмотреть URL] have a look here, at the moment I need only labaa 3. maybe you have to download the fi...

    $23 (Avg Bid)
    $23 Ср. ставка
    2 ставки

    DVLSI project 'ASIC design of face detection using haar wavelet'. Use verilog, FPGA and Viola Jones algorithm

    $298 (Avg Bid)
    $298 Ср. ставка
    2 ставки
    Operating System Computer Engineer Заканчивающийся left
    ПОДТВЕРЖДЕН

    need an operation system engineer to help in mathematical CPU process

    $153 (Avg Bid)
    $153 Ср. ставка
    6 ставки