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    LUT optimization of FFT 6 дней(-я) left

    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

    FPGA Verilog / VHDL Very-large-scale integration (VLSI)
    $147 (Avg Bid)
    $147 Ср. ставка
    2 ставки
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    Fixing 4-bit carry look ahead using VLSI magic 5 дней(-я) left

    Hi, I have a problem with my project, I built everything with a problem with one of the bits sum like s0 s1 s2 s3, I am having issue with s2 , it's giving me unknown and I have a carry in which is not identified anyone with a good experience with VLSI should fix it smoothly. I attached IRSIM analyzer photo to illustrate the issue.

    Схемотехника Электротехника Электроника Техника Very-large-scale integration (VLSI)
    $113 (Avg Bid)
    $113 Ср. ставка
    4 ставки
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