We have a HW card already built that captures data and stores it inside the LSRAM of Microsemi Polarfire FPGA. We use double buffering technique so while capturing new data in one buffer the other buffer is sending the data to the host from the other buffer.
The host has to capture the data in real time. For that, the Host PCIE has to allocate multiple buffers (e.g. cyclic Fifo) so the copied data will be dumped there and the CPU will be using polling mechanism to read and process the received data. The buffer size is upto 518Kbits and has to be transferred in about 200usec .
The CPU will be also sending data (commands) to the FPGA . For that we will use a similar technique of double buffering at teh host side and a cyclic Fifo at the FPGA side.
The project is to deliver the PCIE driver that is capable of performing this task. Microsemi have a Demo that can be used for this matter:
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Expertise in Windows PCIE driver development as well as Microsemi FPGA are very desired to perform this project.