В работе

Verilog module for DAC interface & SPI configuration

We have existing hardware based on

Xilinx XC7K160T-2FFG676

and TI DAC5682ZIRGC25

We want a verilog interface that accepts 32bit axi stream and is capable of speeds in excess of 400Msps. If needed, the internal interface can be 64bit axi stream on half the sample rate, but the external data rate to the DAC must be 400MSps or higher.

A 2nd module must contain the SPI interface for the DAC.

A static configuration that operates the DAC in "normal" operation is sufficient.

For both modules - data interface and SPI interface - we want dedicated test benches being delivered at the end of the project.

We will provide pinout files for the existing hardware.

Vivado 2016.4

Квалификация: Электроника, FPGA, Verilog / VHDL

Показать больше spi protocol, spartan 6 fpga projects, spi verilog code, video over spi, dac verilog code

О работодателе:
( 3 отзыв(-а, -ов) ) Graz, Austria

ID проекта: #19013533

Поручен:

erenss

Hi I am an European freelancer having 5 6 years of experience on fpgas using VHDL and verilog. in the past, i designed some high speed ADC and dac systems and lnterfaces using 7 series xilinx fpgas. please take a look Больше

€750 EUR за 5 дней(-я)
(9 отзывов(-а))
3.8

6 фрилансеров(-а) в среднем готовы выполнить эту работу за €845

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using verilog and I can do the required design, please message me so that we can discuss Best regards

€800 EUR за 10 дней(-я)
(403 отзывов(-а))
7.8
sofiadubina99

Dear Sir. How do you do? I have seen your description very carefully and posting to you my idea. You can check my profile. I made the velriog code for xillinx FPGA and i am using Vivado 2018.3 If you give me a chanc Больше

€800 EUR за 12 дней(-я)
(27 отзывов(-а))
6.4
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Больше

€1111 EUR за 10 дней(-я)
(84 отзывов(-а))
6.3
vlsirajagopal

having more than 8 yrs of experience in verilog/vhdl design and verification. worked on axi interface and spi development as well. I can do this without any functional issues. I have sufficient experience in uvm system Больше

€1111 EUR за 10 дней(-я)
(23 отзывов(-а))
5.4
jyq12356

Much experience in digital IC design. Had done some dac project, mainly charge of interface. Familiar with spi module. This won’t be difficult for me to complete.

€500 EUR за 10 дней(-я)
(0 отзывов(-а))
0.0