VHDL Verification Engineer -- 2

Закрыт Опубликован 4 мес. назад Оплачивается при доставке

Campera Electronic Systems is planning to introduce a Verification methodology in the company verification flow for VHDL designs.

Previous experience on one of the "standard" VHDL verification methodologies (UVVM, OSVVM) or framework (Vunit) is requied.

Техника Электроника Verilog / VHDL Электротехника FPGA

ID проекта: #36673609

О проекте

7 заявок(-ки) Удаленный проект Последняя активность 2 мес. назад

7 фрилансеров(-а) готовы выполнить эту работу в среднем за €30/час


Hi there,I'm biddin on your project "VHDL Verification Engineer -- 2"Verilog / VHDL, FPGA, Engineering, Electrical Engineering and Electronics Campera Electronic Systems is planning to introduce a Verification methodol Больше

€46 EUR / час
(41 отзывов(-а))

Hi there

€27 EUR / час
(4 отзывов(-а))

Dear Andrea C. We went through your project description and it seems like our team is a great fit for this job. We are an expert team which have many years of experience on Engineering, Electronics, Verilog / VHDL, E Больше

€27 EUR / час
(1 отзыв)

I am excited to submit my proposal for the job opening at Campera Electronic Systems, where you are seeking a professional with experience in implementing verification methodologies for VHDL designs. Having extensive k Больше

€23 EUR / час
(0 отзывов(-а))

I am a student from Indian Institute of Technology (IIT) Jodhpur with Computer Science and Engineering branch. I have been interested in Digital Electronics and have also completed a course in it with A grade. I would Больше

€20 EUR / час
(0 отзывов(-а))