Hi, I am looking for help with a VHDL project. Project is create a combinational lock system using VHDL. Lock will open when entered passcode is correct and message "O" will be display on LCD. If entered passcode is not correct, then lock will not open and message "L" will be displayed on LCD. If user enters wrong passcode more than 2 times, then RED LED should Blink. VHDL code should also allow the user to change password. I am using Xilinx ISE Design Suite 14.7 and Vertex 5 XC5VLX50 board to do the demo to my instructor. I am have started it using a State Machine.
Please help by adding/improving the attached code.
I need it very urgently.