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Simple computer architecture and simulation using MaxPlus

Description: Following the lecture presentation and analysis of a simple computer architecture for a highly idealized machine each project group is to complete a design and simulation using MaxPlus software. The architecture will include all detailed circuits to represent the RAM, the CPU and the bus (both data and address). These circuits will be chosen from existing modules supported by MaxPlus (e.g. registers, decoders, multiplexers), or constructed from simpler components (e.g. flip-flops). The RAM must consist of at least 8 words, each 16 bits wide, up to a maximum of 4096 words (this is not expected to be implemented). Consequently, CPU registers IR, AC and DR each 16 bits; PC and AR both 12 bits permitting access to a RAM of up to 4096 words (4096 = 2^12, hence 12 bits is enough to address the available space). Using built-in modules within MaxPlus, you may have to use only a subset of available bits within the modules. Note that the IR uses the low order 12 bits for the address field, the next 3 higher bits for the OpCode and the highest order bit, the I-bit, to designate indirect addressing mode.

## Deliverables

RAM: The memory may consist of up to a maximum of 4096 words, each word being 16 bits. You may implement fewer words, but each must be 16 bits. MaxPlus may not supply a complete memory unit, so it may be necessary to first construct a standard unit using flip-flops (such as D-flip-flop) together with additional circuitry to enable/disable reads and writes to RAM. The RAM must be integrated with the Address and Data Buses as well. Note that the first address of RAM must be zero (0). You should try to build circuitry that detects when an attempt is made to access a RAM address that does not exist, and produces a trigger that, in principle, could be used to generate a report; you should devise a strategy of how to handle such cases if they arise. CPU: he central processing unit (CPU) contains several modules, all interconnected through an internal bus architecture. The registers consist of: Register Bit width Properties AR 12 Used to hold the address of a RAM location and provide input to the address bus multiplexer unit. PC 12 When used properly, this register is used to hold the address of the next executable instruction. It is updated at least once during the instruction cycle, but may be updated additionally (through branch type instructions). DR 16 Used to hold data fetched from RAM into CPU, or from CPU to RAM. IR 16 Used for holding instructions fetched from RAM through DR. The low order 12 bits (0..11) are used to hold a RAM address for memory referencing instructions or an additional instruction discriminating code for register referencing instructions. The bits 12..14 are used to hold the main part of the instruction OpCode. Bit 15, the highest order bit, is used to store the I-Bit used to designate indirect addressing mode discussed in Project 1A. AC 16 Used for data processing. Read/Write enable, INC, CLR, CMP enable inputs. SC 4 Provide up to 16 timing signals. CLR and INC enable inputs. NOTES: INC - increment CLR - clear to zero CMP - complement Read - enable copying (output) of data from register Write - enable copying (input) of data to register Additional registers may be introduced, but are not required. Such registers would require additional logic in the CPU/ALU. Control Unit:The CU is intended to handle the tasks of producing enable/disable signals to the various components of the computer. These signals include Read/Write enable signals to RAM and various CPU registers, as well as special enable signals for INC, CLR and CMP, etc., for specific CPU registers. Arithmetic Logic Unit: The ALU will contain all the circuits required to support the instructions that cannot be implemented through enable logic attached to the registers themselves. For instance, CMA performs complementation of the AC register and this instruction can be implemented by applying a control signal directly to the AC CMP-enable input. On the other hand, ADD does require its own circuit in the ALU. Instruction Set:The instruction set for the machine should consist of instructions defined in Project 1A. Bus:There are two buses - the address bus and the data bus. The address bus is constructed using multiplexer logic tied to the AR register and the appropriate read/write-enable logic. The data bus permits copying of data from the addressed RAM location to the DR register, or vice versa. INTEGRATION:All components from RAM, CPU and Bus must be integrated together to produce a complete working computer. This requires all "wiring" to be completed between all components. This must be described fully in your project submission. Testing:Before submitting your work you must test it to determine if it works according to specifications and requirements. You must describe how you have tested the work in your submission

## Platform

It should run with MAX2Plus

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ID проекта: #3464732