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Design a baseline H.264 encoder with Verilog so that it can be complied and synthesized in Xilinx or Quartus II

Some details:

1. The encoder should include intra mode and inter mode

2. The encoder can encode I frame and P frame.

3. CAVLC is used for entropy encode

4. RDO mode should be implemented and can be chosen based on needs

5. The encoder should have a design to compute the PSNR of YUV components.

6. The code should have notes to help me understand your design.

7. The project should be simulated and synthesized in QuartusII or Xilinx.

8. You should write a document to describe the target and design principle of each module and the relation between different modules.

9. The input of the encoder is a video with QCIF resolution.

10. The output is .264 bits stream. This stream can be decoded correctly with ffmpeg.

11. The last but most important, the encoder should be implemented in Verilog.

Навыки: Цифровой дизайн, FPGA, PHP, Архитектура ПО, Verilog / VHDL

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О работодателе:
( 0 отзыв(-а, -ов) ) Korea, Republic of

ID проекта: #12023739

11 фрилансеров(-а) в среднем готовы выполнить эту работу за $950

SevenStarInfo

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RaspberryOculus

Dear sir, I have experience with video codecs and FPGA both, I use xilinix and spartan 6 & cyclone -4 boards for development.

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kulwantsingh16

A proposal has not yet been provided

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emworld

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