VHDL project: Measuring time between two input signals

I need a simple VHDL program for measuring the time between two input signals.

The VHDL program should be in structural code and should includes modules like Counter, BCDtoASCI, UART and FStateMachine + top level.

I need also for every module and for the hole program testbenches.

Квалификация: FPGA, Микроконтроллер, Архитектура ПО, Verilog / VHDL

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О работодателе:
( 0 отзыв(-а, -ов) ) Friedrichshafen, Germany

ID проекта: #20022535



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