compression and decompression vhdl code

Using the VHDL, design and implement the chips for data compression and data decompression shown in the

following figure. The data compression chip will be implemented in the satellite to compress the data received

from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data

decompression chip will be implemented in the ground station in order to decompress the data received in the

ground station, then it will be analyzed in the computer. The proposed data compression in this work is the LZ

data compression algorithm

Навыки: Verilog / VHDL, Matlab and Mathematica, Электротехника, Программирование на C++, FPGA

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О работодателе:
( 0 отзыв(-а, -ов) ) cairo, Egypt

ID проекта: #28922306

4 фрилансеров(-а) готовы выполнить эту работу в среднем за $170

(463 отзывов(-а))

Expert in Cadence, T-Spice, P-Spice, Communication protocols. Assembly programming, FPGA, Enbedded etc. I can do this work. Pls send a msg to discuss further.

$140 USD за 7 дней(-я)
(21 отзывов(-а))

I think my bide is late but i am a VHDL developer and I can do this task. in Fact i have worked on Similar projects and I can do this task perfectly. Contact me

$200 USD за 7 дней(-я)
(1 отзыв)

I read your job description and wish to contribute to it based on skills as an Electronics and telecommunication engineering student. I believe that my skills in VHDL and MATLAB will be immensely helpful for the task.

$89 USD за 15 дней(-я)
(0 отзывов(-а))