• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
• Understanding of verification tools like Simulator, Synthesis etc.
• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
• Excellent written and verbal interpersonal skills
• Self-motivated and great teammate
9 фрилансеров(-а) готовы выполнить эту работу в среднем за $54/час
working as rtl trainee... hope i would be a great choice for your requirements..i have great amount of knowledge in verilog and good amount of knowledge in sv as well.