Xilinx FPGA-based implementation of the parameterized delay line with good resolution, say in steps of 10ps and good delay range say 512 steps and with minimum FPGA resources say less than 2% utilization.
1. RTL code in Verilog/SV/VHDL and Xilinx Syntheis scripts
2. TB and Verification environment (with parameters) and results
3. Documentation with Architecture Diagram, Algorithm with Flow chart etc
11 фрилансеров(-а) готовы выполнить эту работу в среднем за $425
Dear sir, I am a digital design engineer, expert in Verilog and VHDL programming. Also, I am experienced with Vivado, Vivado IPs, and others. I am interested to do your project. Please contact me to know more details.
Hi, Currenty i am working as FPGA engineer and i am working on the Xilinx's FPGA. I want to update my skills and work on the different projects. I am very interested to work on this project. Please share more details.
I am currently pursuing my Masters in electrical engineering and have developed great expertise in FPGA programming. I am willing to work on your project. Looking forward for a positive response. Regards