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To simulate RTL Design of GCD of two numbers in Verilog using Xilinx ISE.

Бюджет $10-30 USD

Design a GCD for two 4-bit numbers (in your lecture notes, we have already done this). It will output the binary value of the greatest common divisor of those two 4-bit numbers.

Навыки: Verilog / VHDL, FPGA, Микроконтроллер, Электротехника, Техника

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( 10 отзыв(-а, -ов) ) Delhi, India

ID проекта: #29397033

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8 фрилансеров(-а) готовы выполнить эту работу в среднем за $29

Изображение профиля ahmedmohamed85
ahmedmohamed85

(468 отзывов(-а))
8.0
Изображение профиля atharbaig6167
atharbaig6167

(25 отзывов(-а))
4.4
Изображение профиля moaazkh96
moaazkh96

hi, I am a senior digital design engineer, I have a wide knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE and Quartise. I will provide you a professional report about y Больше

$50 USD за 7 дней(-я)
(23 отзывов(-а))
4.2
Изображение профиля jasnaikaran
jasnaikaran

Hello, I am an FPGA design engineer having experience of verilog/vhdl based FPGA system design for more than 5 years.

$20 USD за 1 день
(15 отзывов(-а))
4.1
Изображение профиля kundanvaghela
kundanvaghela

i have 2.5+ year experience in design and verification, i have done 30+ project in verilog/VHDL, i will done your project perfectly and on time, i will provide support after completion of project, thanks and regard Больше

$20 USD за 1 день
(12 отзывов(-а))
3.6
Изображение профиля LancingJobs
LancingJobs

Being an electrical engineer and having strong verilog experience i am bidding on this project, i can do this project for you in cheepest rates, you may contact me with further details

$20 USD за 7 дней(-я)
(4 отзывов(-а))
1.6
Изображение профиля kishan2097
kishan2097

I am an electronics engineer. I am an expert in verilog and FPGA. I have lots of experience with verilog and fpga. I have used vivado, xilinx ise, vitis, quartus and libero softwares for verilog. I have designed 128 bi Больше

$10 USD за 1 день
(0 отзывов(-а))
0.0
Изображение профиля vyasmohit0508
vyasmohit0508

I am a graduate from BITS Pilani, where I have worked with FPGA design in-depth. From being the Teaching assistant in Verilog Design lab to having completed a Graduate course on FPGA design to writing the entire image- Больше

$25 USD за 1 день
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0.0

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