VHDL compression and decompression

Using the VHDL, design and implement the chips for data compression and data decompression shown in the

following figure. The data compression chip will be implemented in the satellite to compress the data received

from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data

decompression chip will be implemented in the ground station in order to decompress the data received in the

ground station, then it will be analyzed in the computer. The proposed data compression in this work is the LZ

data compression algorithm.

Навыки: Verilog / VHDL, FPGA, Электротехника, Matlab and Mathematica, Техника

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ID проекта: #28923164