With Bachelor's in Computer Engineering, I'm Having a high passion for a wide-range understanding of complex systems/solutions from the very high level of OSes and Architecture down to the very low level of IC design and FPGA. I’m actively seeking challenging projects in digital hardware Design/Verification where my skills, work experience, and academic background can significantly both contribute to future technologies enablement and be developed
Working on RTLs written in both VHDL and Verilog
Knowledgeable of Design Methodologies like Power-Aware Design, CDC & DFT.
Knowledgeable of Back-End flow like Clock Tree Synthesis, Placement & Routing.
Knowledgeable of Verification Methodologies Both UVM & System Verilog.
Scripting using: TCL.
Design and Simulation Tools: Modelsim - Xilinx ISE Design Suite- Intel Quartus prime-
Cadence Virtuoso- Synopsys Design Compiler- Cadence SOC Encounter.
Very reliable, precise, accurate and detailed with the results.
It was very pleasant to work with him and I will definitely work with him again.
Everyone who works with Zyad can rely on him and be sure that the tasks will be done to the maximum!
A true professional with vast knowledge.
Very nice work. Zyad did some VHDL programming for me, and he was very committed to a good final product. I'm also grateful for his patience and good communication. The job was tricky in many ways and he came up with some rather clever solutions to make the final product work well.
Acquired knowledge and hands-on experience in:
ASIC Front-End Flow:
• Efficient RTL Coding Using Verilog language
• Building Advanced Self-Checking Test-bench
• TCL Scripting Language
• Static Timing Analysis
• Low Power Design Techniques
• Clock Domain Crossing
ASIC Back-End Flow including:
• RTL Synthesis on Design Compiler
• Design For Testing (DFT) Insertion
• Floorplanning, Placement & Routing.
• Clock Tree Synthesis.
• Timing Closure, Chip Finishing, Sign Off
Digital Hardware Verification Intern.
июн. 2021 - окт. 2021 (4 месяца, 2 дня)
Acquired knowledge and hands-on Experience in:
• System Verilog.
• Universal Verification Methodology (UVM).
Project: Verification environment.
Designing a verification environment for an AES 128 Encryption Engine using UVM based methodology.
Bachelor of Computer Engineering
Ain Shams University, Egypt 2018 - 2022
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