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ASIC Electronics FPGA Microcontroller Verilog / VHDL
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Аватарка пользователя
$20 USD / час
Флаг EGYPT
obour city, egypt
$20 USD / час
Сейчас здесь 1:45 PM
На сайте с сентября 20, 2016
0 Рекомендации

Zyad Sobhy M.

@ZyadSobhy

monthly-level-two.svgpreferred-freelancer-v2.svg
5,0 (9 отзывов(-а))
4,3
4,3
$20 USD / час
Флаг EGYPT
obour city, egypt
$20 USD / час
100 %
Завершенных работ
98 %
В рамках бюджета
100 %
Своевременно
20 %
Рейтинг повторного найма

Digital ASIC/SOC/FPGA Designer/Verification Eng.

With Bachelor's in Computer Engineering, I'm Having a high passion for a wide-range understanding of complex systems/solutions from the very high level of OSes and Architecture down to the very low level of IC design and FPGA. I’m actively seeking challenging projects in digital hardware Design/Verification where my skills, work experience, and academic background can significantly both contribute to future technologies enablement and be developed Skills: Working on RTLs written in both VHDL and Verilog Knowledgeable of Design Methodologies like Power-Aware Design, CDC & DFT. Knowledgeable of Back-End flow like Clock Tree Synthesis, Placement & Routing. Knowledgeable of Verification Methodologies Both UVM & System Verilog. Scripting using: TCL. Design and Simulation Tools: Modelsim - Xilinx ISE Design Suite- Intel Quartus prime- Cadence Virtuoso- Synopsys Design Compiler- Cadence SOC Encounter.
Freelancer Verilog / VHDL Designers Egypt

Свяжитесь с Zyad Sobhy M. по поводу вашей работы

Авторизуйтесь для обсуждения любых деталей в чате.

Элементы портфолио

Pipelined RISC-V in VHDL
Pipelined RISC-V in VHDL with 35+ instructions
Pipelined RISC-V in VHDL
Pipelined RISC-V in VHDL with 35+ instructions
Pipelined RISC-V in VHDL
Pipelined RISC-V in VHDL with 35+ instructions
Pipelined RISC-V in VHDL
Pipelined RISC-V in VHDL with 35+ instructions
Pipelined RISC-V in VHDL
Pipelined RISC-V in VHDL with 35+ instructions
Generate Various Signals to Set, Reset and Read Memristors using FPGA
Generate various signals to control Memristors using FPGA
Generate Various Signals to Set, Reset and Read Memristors using FPGA
Generate various signals to control Memristors using FPGA
Generate Various Signals to Set, Reset and Read Memristors using FPGA
Generate various signals to control Memristors using FPGA
Pipelined MIPS Processor on Logisim associated with hazard unit
Pipelined MIPS Processor on Logisim
Thermometer System on Chip
Thermometer System on Chip in Verilog (SOC)
	Description: It is responsible of receiving commands through UART receiver to do different system functions as register file reading/writing or doing some processing using ALU block and send result as well as CRC bits of result using 4 bytes frame through UART transmitter communication protocol.                 
	Project phases: -
	RTL Design from Scratch of system blocks (ALU, Register File, Synchronous FIFO, Integer Clock Divider, Clock Gating, Synchronizers, Main Controller, UART TX, UART RX).
	Integrate and verify functionality through self-checking testbench. 
	Constraining the system using synthesis TCL scripts.
	Synthesize and optimize the design using design compiler tool.
	Analyze Timing paths and fix setup and hold violations.
	Verify Functionality equivalence using Formality tool
	Physical implementation of the system passing through ASIC flow phases and generate the GDS File.
	Verify functionality post-layout considering the actual delays.
RTL to GDS Implementation of Low Power Configurable Multi
Universal Asynchronous Receiver-Transmitter
Universal Asynchronous Receiver-Transmitter
Universal Asynchronous Receiver-Transmitter
Universal Asynchronous Receiver-Transmitter

Отзывы

Изменения сохранены
Показаны с 1 по 5 из 9 отзывов
Фильтровать отзывы по: 5,0
$600,00 USD
Very reliable, precise, accurate and detailed with the results. It was very pleasant to work with him and I will definitely work with him again. Everyone who works with Zyad can rely on him and be sure that the tasks will be done to the maximum! A true professional with vast knowledge.
Electronics Verilog / VHDL Microcontroller Assembly FPGA
M
Флаг Nemanja M. @montana0110
6 месяцев назад
5,0
$140,00 USD
Zyad is a very honest and hardworking person. One thing about him is he delivers on time and he does what he says. He is an expert in his field and is very knowledgeable.
Electronics Verilog / VHDL Microcontroller FPGA
+ еще 1
R
Флаг Abdur C. @rarbararba
8 месяцев назад
5,0
$65,00 USD
Very nice work. Zyad did some VHDL programming for me, and he was very committed to a good final product. I'm also grateful for his patience and good communication. The job was tricky in many ways and he came up with some rather clever solutions to make the final product work well.
Electronics Verilog / VHDL Microcontroller FPGA
+ еще 1
Аватарка пользователя
Флаг Mostafa H. @mostafahesham194
9 месяцев назад
5,0
£190,00 GBP
I gave zyad a task and he finished it within 5-6 hours, he solved the task perfectly.
Electronics Verilog / VHDL Microcontroller FPGA ASIC
Z
Флаг Zahra S. @zahrash13
9 месяцев назад
5,0
$200,00 USD
Has great communication skills and works hard to get the work done. Very friendly and nice to work with.
Electronics Verilog / VHDL Microcontroller FPGA
+ еще 1
Аватарка пользователя
Флаг Nicholas D. @Nick3445
9 месяцев назад

Опыт работы

ASIC Design Intern

Synopsys
дек. 2021 - Настоящее время
Acquired knowledge and hands-on experience in:  ASIC Front-End Flow: • Efficient RTL Coding Using Verilog language • Building Advanced Self-Checking Test-bench • TCL Scripting Language • Static Timing Analysis • Low Power Design Techniques • Clock Domain Crossing  ASIC Back-End Flow including: • RTL Synthesis on Design Compiler • Design For Testing (DFT) Insertion • Floorplanning, Placement & Routing. • Clock Tree Synthesis. • Timing Closure, Chip Finishing, Sign Off

Digital Hardware Verification Intern.

Siemens
июн. 2021 - окт. 2021 (4 месяца, 2 дня)
Acquired knowledge and hands-on Experience in: • System Verilog. • Universal Verification Methodology (UVM).  Project: Verification environment. Designing a verification environment for an AES 128 Encryption Engine using UVM based methodology.

Образование

Bachelor of Computer Engineering

Ain Shams University, Egypt 2018 - 2022
(4 года)

Свяжитесь с Zyad Sobhy M. по поводу вашей работы

Авторизуйтесь для обсуждения любых деталей в чате.

Верификация

Предпочтительный фрилансер
Личность подтверждена
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Связано с Facebook

Сертификаты

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Топ-навыки

Verilog / VHDL 9 Electronics 8 Microcontroller 7 FPGA 7 ASIC 5

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